Integrated circuit and method of forming semiconductor structure

Abstract

The embodiment of the invention provides an integrated circuit and a method for forming a semiconductor structure. The gate-all-around (GAA) nanowire transistor is provided with a plurality of nanowire channels which are vertically stacked, a first grid dielectric layer wrapping the nanowire channels and a first grid electrode wrapping the first grid dielectric layer. The GAA nanowire transistorshas a plurality of vertically stacked nanosheet channels, a second gate dielectric layer wrapping the nanosheet channels, and a second gate electrode wrapping the second gate dielectric layer. The planar device has a planar channel, a third gate dielectric layer on the planar channel, and a third gate electrode on the third gate dielectric layer. The first and second gate dielectric layers have the same thickness. The third gate dielectric layer is thicker than the first and second gate dielectric layers. The widths of the nanowire channels and the nanosheet channels are smaller than the widthof the planar channel.

Description

technical field [0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a wrap-around gate device and a planar device. Background technique [0002] Vertically stacked gate-all-around (GAA) horizontal nanowire (NW) and nanosheet (nanosheet, NS) devices are promising next-generation integrated circuits (ICs) because of their Good gate controllability, low leakage and good scalability. The GAA NW device and the GAA NS device have multiple vertically stacked wire channels and sheet channels, respectively, in their channel region, which are wrapped by gate dielectric layers and gate electrodes. The vertical space between adjacent wire channels or sheet channels limits the thickness of the gate dielectric layer. Therefore, GAA NW devices and GAA NS devices may not be suitable for certain applications requiring thick gate dielectric layers, such as input / output (I / O) functions. Improvements are needed in this area....

AI Technical Summary

Problems solved by technology

The vertical space between adjacent wire channels or sheet channels limits the thickness of the gate dielectric layer

Therefore, GAA NW devices and GAA NS devices may not be suitable for certain applications that require thick gate dielectric layers, such as input / output (I / O) functions

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