MOS transistor with elevated source and drain structures and method of fabrication thereof

Abstract

A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source / drain extension regions, the source / drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source / drain regions and the source / drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

Description

RELATED APPLICATIONS [0001] This application is a divisional of U.S. application Ser. No. 10 / 697,826, filed on Oct. 30, 2003, which relies for priority upon Korean Patent Application No. 03-12793, filed on Feb. 28, 2003, the contents of which are herein incorporated by reference in their entirety.BACKGROUND OF INVENTION [0002] the semiconductor industry, minimization of the feature size of MOS transistors in integrated circuits is a common goal. This goal is essentially driven by the need to produce integrated circuits at ever-lower costs, while improving circuit functionality and speed. Such downscaling can be achieved by reducing the characteristic dimensions of the transistors, i.e. reducing the gate lengths, the gate oxide thickness, and the junction depths, and by increasing the channel doping levels. However, scaled-down MOS transistors generally suffer from a phenomenon referred to as the “short-channel effect”. The short-channel effect has an adverse impact on the switching ...

AI Technical Summary

Benefits of technology

The present invention provides a MOS transistor with elevated source and drain structures that overcomes limitations of conventional embodiments. By elevating the source and drain extension regions into the epitaxial layer and controlling the geometries of the source and drain regions, the effective channel length is increased while limiting dopant diffusion into the channel region. The performance characteristics of the transistor can be accurately determined by controlling the geometries of the source and drain regions, insulating spacers on sidewalls of the gate electrode, and the dopant concentration in the epitaxial layer. The invention also provides a method for forming the MOS transistor with elevated source and drain structures. The technical effects of the invention include improved performance and reliability of the MOS transistor.

Problems solved by technology

However, scaled-down MOS transistors generally suffer from a phenomenon referred to as the “short-channel effect”.

The short-channel effect has an adverse impact on the switching performance of the transistors, because such switching is inefficiently controlled by the gate electrode, which leads to an undesired decrease in the threshold voltage.

A problem lies in that impurities in the source / drain extension regions 106a / 106b tend to diffuse to the region immediately under the gate 110.

This inhibits the flow of electric current, thus decreasing operation speed.

A second problem concerns the rise of channel dopant concentration, which in turn causes a rise in threshold voltage in the field effect transistor.

For this reason, any rise in the threshold voltage of MOS transistor due to the rise in channel dopant concentration is undesirable.

On the other hand, a channel doping level that is too high in scaled-down devices gives rise to superfluous leakage current and junction breakdown.

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