Pre-anneal of cosi, to prevent formation of amorphous layer between ti-o-n and cosi
Patent Information
- Authority / Receiving Office
- US ยท United States
- Current Assignee / Owner
- GLOBALFOUNDRIES INC
- Publication Date
- 2005-03-31
- Estimated Expiration
- Not applicable ยท inactive patent
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Abstract
Description
FIELD OF INVENTION
[0001] The present invention relates to semiconductor devices and a method of manufacture, more particularly to an improved via interconnect to a silicide region. BACKGROUND OF THE INVENTION
[0002] Barrier layers and silicide layers are often an integral part of semiconducting devices. Materials which function as barriers to metal diffusion may be incorporated in metal interconnect structures that are part of integrated circuits (ICs). Barriers to metal diffusion are typically required to generate reliable devices, since low-k interlayer dielectrics typically do not prohibit metal diffusion.
[0003] Silicide contacts are of specific importance to IC's, including complementary metal oxide semiconductor (CMOS) devices because of the need to reduce the electrical resistance of the many Si contacts, at the source / drain and gate regions, in order to increase chip performance. Silicides are metal-silicon compounds that are thermally stable and provide for low electrical ...