Patents
Literature
Patsnap Eureka AI that helps you search prior art, draft patents, and assess FTO risks, powered by patent and scientific literature data.

4results about How to "Increase the current level" patented technology

Electrodeionization separation and purification method applied to desalination process of bio-based product

The invention discloses an electrodeionization separation and purification method applied to a bio-based product desalination process, and belongs to the technical field of biochemical engineering separation. According to the electrodeionization separation and purification method applied to the desalination process of the bio-based product, the advantages of electrodialysis and resin desalination are fused, the resistance between the electrode plates is effectively reduced through the built-in medium containing the ionic groups, then the desalination efficiency driven by current is enhanced, and the production cost is reduced. According to the method, an electrodeionization device is utilized, efficient desalination treatment is carried out on various bio-based products such as saccharides and derivatives thereof, organic acid and organic alcohol, the desalination efficiency generally exceeds 98%, and the unit yield is kept to be 95% or above. In addition, under the configuration of a product flow conveyed across the membrane and a specific membrane group, the technology also shows excellent decolorization performance. The method disclosed by the invention shows wide applicability in desalting treatment of bio-based products, which indicates that the method has a wide development prospect in industrial application.
Owner:BEIJING UNIV OF CHEM TECH

A low-inductance packaging structure and packaging method for a power semiconductor module

ActiveCN113035847BReduce electromagnetic oscillationImprove reliabilitySemiconductor/solid-state device detailsSolid-state devices
The present invention relates to the technical field of power semiconductor modules, and proposes a low-inductance packaging structure of a power semiconductor module, comprising a substrate and a power semiconductor module unit arranged on the substrate, the power semiconductor module unit is used to form a dual-switch circuit structure capable of reducing inductance, the power semiconductor module unit comprises a plurality of lining plates arranged at intervals on the substrate, adjacent lining plates are connected by a first bonding wire, two connected lining plates are connected with a power terminal group extending out of an outer tube shell, the power terminal group comprises two sub-power terminals which are partially overlapped but not in contact with each other, and are used to generate electromagnetic coupling when the two sub-power terminals conduct currents in different directions to reduce inductance; a low-inductance packaging method of a power semiconductor module is also proposed, which is used to manufacture the low-inductance packaging structure of a power semiconductor module proposed by the present invention. The present invention has the advantages of high reliability, high power density and low inductance.
Owner:ZHUZHOU CRRC TIMES SEMICON CO LTD

Semiconductor power module and power device

ActiveCN116053246BReduce thermal resistanceIncrease the current levelThermodynamicsSemiconductor
The application provides a semiconductor power module and a power device, the power module comprising a backing plate, the surface of the backing plate having a plurality of metal layers arranged in sequence along a first direction, the metal layers comprising at least a first metal layer, a second metal layer and a third metal layer arranged in sequence; the first metal layer and the third metal layer are strips extending along a second direction perpendicular to the first direction, the second metal layer is adjacent to the first metal layer and the third metal layer, and the widths of the second metal layer and the backing plate in the second direction match each other. Based on the technical scheme of the application, the number of small-area metal islands is reduced and integrated by layout design of the metal layers, the utilization rate of the surface space of the backing plate is improved, the area of one of the at least metal layers is maximized as a chip welding area, thereby reducing the thermal resistance of the device, improving the current level of the device, and meeting the requirements of the semiconductor power module for bearing large current and high voltage.
Owner:ZHUZHOU CRRC TIMES SEMICON CO LTD

Tunneling field effect transistor, preparation method thereof and photoelectric detector

The invention provides a tunneling field effect transistor, a preparation method thereof and a photoelectric detector, and relates to the field of photoelectric devices.The tunneling field effect transistor comprises a substrate, an insulating layer, a conductive layer, a dielectric layer, a heterojunction layer and a packaging layer, the heterojunction layer comprises a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is stacked on the dielectric layer, at least part of the second semiconductor layer is stacked on the first semiconductor layer, and the other part of the second semiconductor layer is stacked on the dielectric layer; the first semiconductor layer comprises a tin disulfide layer, the second semiconductor layer comprises a hafnium disulfide layer, and the encapsulation layer comprises a hafnium oxide layer. According to the invention, the plasma oxidation technology is adopted to package hafnium disulfide with ultrahigh carrier characteristics, so that a hafnium oxide dielectric layer with a high dielectric constant is formed, a high-quality interface is ensured, the tunneling characteristic of the field effect transistor is realized, and the performance of the field effect transistor is improved. And a foundation is laid for finally realizing a low-power-consumption tunneling device of a high-performance nano material in the future.
Owner:SHENZHEN UNIV