A kind of semiconductor device and its manufacturing method, electronic device

Abstract

The present invention provides a method for manufacturing a semiconductor device, the method comprising: step a: providing a semiconductor substrate; step b: forming an insulating layer having an opening and a silicon layer located in the opening on the semiconductor substrate; Forming a heavily doped region in the opening region and the surface layer of the semiconductor substrate below the opening region; step c: forming a channel region, a gate oxide layer and a gate on the insulating layer; step d: forming a gate on the gate A source region and a drain region are formed on both sides; wherein, the source region and the drain region form a Schottky contact with the channel region. Through the manufacturing method of the semiconductor device of the invention, the self-heating effect, leakage-induced potential barrier lowering effect and subthreshold characteristics of the device can be improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] In the contemporary information society, under the dual drive of maximizing chip integration density and optimizing circuit performance, the core MOSFET devices of integrated circuits are constantly being scaled down. Since the 1970s, due to the development of the ion implantation process, extremely small MOSFETs have been fabricated, and the theory of MOSFET scaling has been established. As the size of MOSFET devices continues to shrink, various small-size effects are gradually revealed. For example, as the channel size continues to decrease, the short-channel effect and the drain-induced barrier lowering (DIBL) effect become increasingly severe, resulting in poor device performance. At the same time, the leakage induced barrier lowering (DIBL) ef...

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Problems solved by technology

For example, as the channel size continues to decrease, the short channel effect and the drain-induced barrier lowering (DIBL) effect are becoming more and more serious, resulting in poor device performance.

At the same time, the leakage-induced barrier lowering (DIBL) effect will affect the sub-threshold characteristics, such as degrading the sub-threshold swing (or S factor). In the scaling rules of large-scale digital integrated circuits, the constant voltage scaling rule , the constant electric field reduction rule, etc. cannot reduce the S value, and the leakage current in the subthreshold region deteriorates the off-state characteristics of the MOSFET device and increases the static power consumption

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