476 results about "Semiconductor device fabrication" patented technology

The invention relates to the technical field of semiconductor device manufacturing, solves the technical problem that in the prior art, automatic grain digging treatment cannot be carried out on detected LED support defective products, and provides a grain digging control method, device and equipment for LED support defective products. Acquiring a real-time image of the to-be-detected LED bracket under a preset target illumination condition; performing visual detection processing on the real-time image, and judging whether the to-be-detected LED bracket is a defective bracket product or not according to a visual detection processing result; when the to-be-detected LED bracket is judged to be a defective bracket product, defect position detection is carried out on the defective bracket product to obtain defect position information; according to the defect position information, defective stent particles in the defective stent products are removed, and particle digging control over the defective stent products is achieved. According to the automatic grain digging device, automatic grain digging treatment can be accurately carried out on the LED support defective products.

The present disclosure provides a method for manufacturing a semiconductor device using selective vapor deposition and selective desorption. The method for manufacturing a semiconductor device includes providing a first layer having a first surface, and forming a second layer on the first layer such that a portion of the first surface is not covered by the second layer. The second layer has a second surface that meets the first surface. An inhibitor layer is formed on the first surface and the second surface, and the inhibitor layer on the second surface is selectively removed to expose the second surface. An interest layer is formed on the second surface. Physical properties of the first layer are different from physical properties of the second layer.

It is possible to economically and safely operate an apparatus by allowing wafers made of different materials to be accommodated together. There is provided a technique that includes: a mapping apparatus configured to determine a material of a substrate accommodated in a carrier and loaded into the substrate processing apparatus; and a controller configured to be capable of updating and holding first information on the material of the substrate loaded into the substrate processing apparatus, and capable of controlling the substrate processing apparatus to take out the carrier accommodating the substrate when the first information on the material of the substrate does not satisfy a predetermined condition specified for a current operation mode among conditions specified respectively for a plurality of operation modes.

The invention relates to the technical field of semiconductor device manufacturing, in particular to an LED chip passivation layer preparation method and structure based on PECVD multi-section deposition, and the method comprises the following steps: providing an LED chip substrate with a light-emitting structure and an electrode formed on the surface; a passivation layer is deposited on the substrate through a PECVD (Plasma Enhanced Chemical Vapor Deposition) process in three stages: in the first deposition stage, an interface bonding layer is deposited and formed under the process conditions of low radio frequency power, high reaction pressure and low silicon-nitrogen gas flow ratio; and in the second deposition stage, a stress buffer layer is deposited and formed on the interface bonding layer under the process conditions of medium radio frequency power, medium reaction pressure and medium silicon-nitrogen gas flow ratio. Through deposition under the conditions of low power, high pressure and rich nitrogen in the first stage, firm combination, mainly based on strong chemical bonding (such as Si-N-Ga), between a passivation layer and a bottom layer (such as GaN) is achieved, and the problems of film layering and blistering caused by a traditional process are fundamentally solved.

A temperature regulating apparatus includes: a heating section configured to produce a heating liquid; a cooling section configured to produce a cooling liquid; a heating-liquid delivery pipe for delivering the heating liquid to the semiconductor-device manufacturing equipment; a cooling-liquid delivery pipe for delivering the cooling liquid to the semiconductor-device manufacturing equipment; a heating-side return pipe for returning a liquid mixture of the heating liquid and the cooling liquid that have passed through the semiconductor-device manufacturing equipment to the heating section; a cooling-side return pipe for returning the liquid mixture that has passed through the semiconductor-device manufacturing equipment to the cooling section; and at least one of a heating-side heat exchanger configured to exchange heat between the heating liquid and the liquid mixture and a cooling-side heat exchanger configured to exchange heat between the cooling liquid and the liquid mixture.

This semiconductor device manufacturing method comprises: a step for preparing a semiconductor module including a main substrate having a back surface that is exposed to the outside; and a step for bonding a main surface of a heat dissipation member and the back surface by diffusion bonding. The step for bonding by diffusion bonding of the manufacturing method includes a process for heating the main surface and the back surface from room temperature to a first temperature range. The manufacturing method comprises, after the step for preparing the semiconductor module and before the step for bonding by diffusion bonding: a step for heating the semiconductor module from room temperature to the first temperature range; and a step for flattening the back surface of the semiconductor module heated to the first temperature range.

To provide a prober capable of accurately and stably bringing a probe needle into contact with a semiconductor chip without measuring a temperature.SOLUTION: A prober 100 generates first tip position data of a probe needle 121 at a predetermined time interval during a successive inspection of a semiconductor chip for constructing a transition pattern DB and further generates transition pattern data by arraying the generated first tip position data in time series. The prober 100 generates a transition pattern data group obtained by changing a preset temperature of a wafer chuck for each of transition pattern data. While semiconductor chips are newly successively inspected, the prober 100 then identifies, from a transition pattern data group, transition pattern data including a portion most similar to sub transition data, which are obtained by arraying second tip position data of the probe needle 121 in every predetermined timing in time series, and corrects a relative position based on the identified transition pattern data.SELECTED DRAWING: Figure 7

Provided is a technique with which it is possible to drive a moving body without waiting for a recognition result.　A mounting apparatus comprises: a moving body; a drive unit that drives the moving body; an imaging device that captures an image of a target position of the moving body; and a control unit that, in parallel with calculation of the target position based on the image that is captured by the imaging device, drives the moving body using the drive unit on the basis of a base target position, and always sets the base target position to a position in front of the calculated target position.

The present invention provides a processing solution for semiconductor devices that excels in suppressing defects, a method for processing substrates, and a method for manufacturing semiconductor devices. [Solution] The present invention provides a processing solution for semiconductor devices, a method for processing substrates, and a method for manufacturing semiconductor devices, all of which contain a quaternary ammonium hydroxide compound, a cyclic ether compound, and an alkyl ketone, wherein the total content of the cyclic ether compound and the alkyl ketone is 0.001 ppm or more and less than 5 ppm.

There is provided a technique that includes a processor configured to be capable of executing a process recipe to process a substrate; and a pressure controller configured to be capable of controlling a pressure of a process chamber, in which the substrate is processed, by adjusting an opening degree of a pressure regulating valve provided to an exhaust line of the process chamber, wherein when controlling the pressure of the process chamber, the pressure controller adjusts the opening degree of the pressure regulating valve and outputs information of the opening degree, and wherein while receiving the information of the opening degree from the pressure controller and monitoring an open / close state of the pressure regulating valve, the processor is configured to, when the information of the opening degree is a preset value, be capable of determining whether or not opening / closing of the pressure regulating valve happens.

A substrate processing method is provided. The substrate processing method comprises loading a substrate onto a substrate support inside a chamber, forming a plasma inside the chamber, providing a first DC pulse signal to an electromagnet that generates a magnetic field inside the chamber and processing the substrate with the plasma, wherein the first DC pulse signal is repeated at a first period including a first section and a second section subsequent to the first section, the first DC pulse signal has a first level during the first section, and the first DC pulse signal has a second level different from the first level during the second section.

To provide a technique capable of selectively processing a desired surface among inner surfaces of a recess formed in a substrate.SOLUTION: (a) providing a substrate having a first end and a second end, the first end defining at least a portion of an inner surface of a recess, the second end being different from the first end; and (b) exposing the substrate to a treatment solution comprising a liquid reactive with the first end and an additive that reduces the surface tension of the liquid, thereby selectively removing the first end relative to the second end.SELECTED DRAWING: Figure 4

To provide a method of manufacturing a semiconductor device capable of improving reliability.SOLUTION: The method includes forming a first mask 100C having a plurality of openings MO on an upper surface divided into a first region 100E and a second region M1, forming a second mask M1 that exposes a portion of the first mask 100C disposed in the first region M1 and covers a portion of the first mask 100E disposed in the second region M2, etching the substrate SUB in the first region M1 using the first mask and the second mask as a mask, removing the second mask, and etching the substrate SUB in the first region and the second region using the first mask as a mask. 100E M2 100C 100C M1 M2.SELECTED DRAWING: Figure 7

To provide a resist pattern forming composition and a method for producing a resist pattern using the same. A resist pattern forming composition is a high-performance material that can be used in a semiconductor device producing step of a nanotechnology process, for example, a step of producing a semiconductor device that controls liquid crystals, quantum dots, or OLED displays formed on a substrate.

The purpose of the present invention is to provide: an etching method with which anisotropic etching of silicon is possible even if a gas having a low GWP is used; a method for manufacturing a semiconductor device; and an etching apparatus. The present invention relates to an etching method for etching silicon at 40°C or lower with use of a plasma gas that is obtained by converting, into plasma, an etching gas composition that contains at least one gas selected from the group consisting of fluorine-containing interhalogens, F2, Cl2, Br2, and I2.　

The purpose of the present invention is to provide a technique capable of grasping the surface state of a sample stage and diagnosing the occurrence of an abnormality.　In order to provide the technique, the diagnostic device according to the present invention which diagnoses the presence or absence of an abnormality of a sample stage on which a sample is placed is characterized in that: the presence or absence of the abnormality of the sample stage is determined on the basis of a time constant in a transient change in the current when static elimination processing is performed; the static elimination processing is processing for detaching, from the sample stage, the sample electrostatically adsorbed on the sample stage; and the current is a current flowing through the sample stage when a voltage for electrostatically adsorbing the sample onto the sample stage is applied to the sample stage.

To provide a temporary protective film that has excellent adhesive strength at room temperature and can suppress remaining on an adherend when peeled off.SOLUTION: A temporary protective film for semiconductor device manufacturing includes a support film and an adhesive layer provided on the support film, the adhesive layer includes a polymer containing alkyl (meth)acrylate, (meth)acryloylmorpholine, and a monomer having a crosslinkable group as a monomer unit, and a crosslinking agent capable of crosslinking with the crosslinkable group, and the content of (meth)acryloylmorpholine is 7 mass% or more based on the total amount of monomer units in the polymer.SELECTED DRAWING: Figure 1

A semiconductor element testing device (100) comprises a stage (1) and a probe (4). A semiconductor element can be mounted on the stage (1). The probe (4) can be in contact with the semiconductor element (2). A surface (10) of the stage (1) includes a first region (Q1). The first region (Q1) is provided with protrusions (11).

A semiconductor device, a method of manufacturing a semiconductor device, and an electronic apparatus are provided. The semiconductor device includes a channel layer including a van der Waals material, a source electrode structure and a drain electrode structure electrically connected to opposite ends of the channel layer, respectively, a gate insulating layer on the channel layer, and a gate electrode on the gate insulating layer, wherein each of the source electrode structure and the drain electrode structure includes an intermediate layer and a metal layer on the intermediate layer, the intermediate layer including one of a semiconductor or an insulator and a dopant.

A semiconductor device of embodiments includes: an electrode containing titanium (Ti); a silicon carbide layer; a first region provided between the silicon carbide layer and the electrode, containing silicon (Si) and oxygen (O), and having a thickness equal to or more than 2 nm and equal to or less than 10 nm; and a second region provided between the first region and the electrode and containing titanium (Ti) and silicon (Si).

Embodiments of the present disclosure generally relate to non-plasma methods of processing a substrate. More specifically, the methods disclosed herein incorporate microwave oxidation that is used to selectively etch materials during semiconductor device manufacturing. The method for etching a semiconductor device structure is disclosed includes performing a microwave oxidation etch process on the semiconductor device structure, wherein a hard mask is disposed over at least a portion of the semiconductor device structure. The microwave oxidation etch process includes flowing a first process gas over the semiconductor device structure and delivering a microwave energy to the first process gas without generating a plasma. The method further includes performing a preclean process on the semiconductor device structure. The preclean process includes flowing a second process gas over the semiconductor device structure.

Provided is a laser processing method for irradiating a target with laser light to perform processing along a virtual surface inside the target which is along a laser light incidence surface of the target, said laser processing method comprising: a first processing step for forming a plurality of modification regions along the virtual surface in a first portion, which is part of the target when viewed from a Z direction that intersects the incidence surface, by irradiating the first portion of the target with laser light along the virtual surface; and a second processing step for, after the first processing step, forming a plurality of modification regions along the virtual surface in a second portion, which is another part of the target when viewed from Z direction, by irradiating the second portion of the target with laser light along the virtual surface.

A manufacturing apparatus (10) for a semiconductor device is provided with: a chip holder (12) for holding a dicing tape (110), to which a plurality of chips (100) are attached, in a posture in which the plurality of chips (100) face downward in a gravity direction; and a pickup tool (20) for picking up, in a non-contact manner, a target chip (100a), which is one of the plurality of chips (100), from a lower side of the chip holder (12).

To provide a method for manufacturing a semiconductor device capable of successfully performing selective etching for a layer to be etched, and a manufacturing device thereof.SOLUTION: A method for manufacturing a semiconductor device includes processing of a substrate including a laminate in which a layer to be protected and a layer to be etched are alternately laminated. The method includes a step of selectively forming a self-assembled monolayer (SAM) on at least a surface of the layer to be protected, and a step of selectively etching the layer to be etched with the SAM as a protection layer. The SAM forming step includes a first contact step, a removal step, a surface modification step, and a second contact step. The first contact step chemically absorbs a SAM molecule by bringing a first process liquid containing the SAM molecule into contact with a surface of the layer to be protected. The removal step removes a SAM molecule which has not been chemically absorbed from the surface of the layer to be protected. The surface modification step surface-modifies a region in which no SAM molecule exists on the surface of the layer to be protected after the removal step into a region which can be chemically absorbed by a SAM molecule. The second contact step chemically absorbs the SAM molecule by bringing a second process liquid containing the SAM molecule and having the same kind or a different kind of the first process liquid into contact with the surface-modified region.SELECTED DRAWING: Figure 3

Semiconductor component manufacturing process, including: a step which provides a wafer source (1) having a first principal surface (2) on one side and a second principal surface (3) on the other side, and a first support element (11) and a second support element (21); a support step with a first support step in which the wafer source (1) is supported on the side of the first main surface (2) by the first support element (11), and with a second support step in which the wafer source (1) is supported on the side of the second main surface (3) by the second support element (21), wherein the second support step includes bonding a first plate surface (22) of the second support element (21) to the second main surface (3) of the wafer source (1) by a direct bonding process, and wherein a second amorphous bond layer (32) is formed between the second main surface (3) and the first plate surface (22) after bonding, the procedure further features: a step of forming a modified layer (33) in which a modified layer (33) is formed along a horizontal direction parallel to the first principal surface (2) in a thickness-direction intermediate section of the wafer source (1); and a wafer separation step in which a wafer structure (35) containing the second support element (21) and a wafer (34) is separated from the wafer source (1) by means of the modified layer (33), wherein the wafer structure (35) with the second support element (21) and the wafer (34) includes the second amorphous bond layer (32) which bonds the second support element (21) and the wafer (34), and wherein the second amorphous bond layer (32) is formed as a starting point for separating the second support element (21) and the wafer (34) in a subsequent step.

This product is an adhesive tape material used in the semiconductor device manufacturing process for dicing semiconductor wafers and die bonding of semiconductor chips obtained by dicing. To use it, the PET separator portion is peeled off, the wafer ring is attached to the adhesive layer, and the semiconductor wafer is attached to the adhesive layer. The adhesive layer of this product is covered by a base material portion and an adhesive layer portion, and has an uneven surface on its outer periphery. The uneven surface on the adhesive layer of this product allows for smooth peeling of the PET separator portion from the adhesive layer portion because the force applied to the outer periphery of the adhesive layer portion is distributed. Furthermore, when the semiconductor wafer is attached to the adhesive layer and then diced while cooled, the outer periphery of the adhesive layer portion breaks along the uneven surface, preventing it from scattering into tiny fragments.

A semiconductor device manufacturing device comprises: a stage; two bonding heads which are mutually independently horizontally movable; and a controller for causing each of the two bonding heads to perform a positioning process for horizontal positioning, a grounding process for lowering the chip until the chip is grounded on a substrate, and a pressurizing process for applying a bonding load to the chip that is grounded. The controller causes the two bonding heads to perform the positioning process and the grounding process independently from each other in a non-pressurizing period in which neither of the bonding heads is performing the pressurizing process, and causes the two bonding heads after completing the positioning process and the grounding process to perform the pressurizing process in parallel.

The present invention comprises: (a) a processing tube including a cylinder portion which has a covered top and which internally accommodates a substrate; (b) a supply buffer which is provided on a side wall of the cylinder portion and which protrudes outward from the side wall; (c) a first injection device which is installed inside the supply buffer and which extends along the direction of an axis of the cylinder portion; and (d) a plurality of exhaust sections which are formed in the side walls of the cylinder portion and which exhaust raw material gas, the plurality of exhaust sections including a pair of exhaust sections opening from both sides of a virtual plane set to pass through the circumferential center of the cylinder portion and the axis of the cylinder portion at a boundary between the supply buffer and the cylinder portion in a plan view.

The present invention relates to a substrate processing method and a system for the same. The substrate processing method comprises the steps of: vaporizing an organic inhibitor compound under reduced pressure from a porous medium impregnated with an organic inhibitor compound; and selectively depositing the vaporized organic inhibitor compound on a first region of the substrate under a first pressure for, for example, a predetermined time in a first chamber containing a substrate to form a self-assembled monolayer containing the organic inhibitor compound on the first region of the substrate.

A semiconductor biologically sensitive semiconductor device fabrication method and structure includes a biosensor microwell or well transistor and a reference electrode transistor; a biosensor microwell or well into which a biological material may be selectively introduced and a reference electrode cavity into which a reference material may be selectively introduced; a biologically sensitive layer within the biosensor microwell or well that is reactive to the biological material; and wherein the reference electrode cavity is located proximate to the biosensor microwell or well.