968 results about "Semiconductor device fabrication" patented technology

The invention belongs to the technical field of semiconductor device manufacturing and processing, and particularly relates to semiconductor device manufacturing processing equipment which comprises a base and a mechanical arm fixedly arranged at the top of the base, a dust removal mechanism is fixedly arranged at one end of the mechanical arm, and a wafer polishing mechanism is fixedly arranged at the bottom end of the dust removal mechanism. A pneumatic lifting mechanism is fixedly arranged at the top of the base, when a wafer clamped by the wafer clamping mechanism needs to be turned over, the clamping air bag is inflated through the air nozzle, the wafer is clamped through the clamping air bag, then a valve on the air outlet is closed, at the moment, the air pressure in the hollow stand column can be continuously increased, and the wafer can be turned over. The piston assembly in the pneumatic lifting mechanism is pushed by air pressure to be jacked upwards, the ejector rod can be synchronously driven to ascend when the piston assembly is jacked upwards, the wafer clamping mechanism can be jacked up synchronously through the ejector rod, a wafer needing to be polished can be turned over conveniently, and the back face of the wafer can be polished conveniently.

The invention discloses an intelligent cutting method and system for a semiconductor machined part based on path reconstruction, and relates to the technical field of semiconductor manufacturing processes, and the method comprises the steps: monitoring a machined part image, and extracting the edge contour and internal feature point information; fitting and constructing a three-dimensional contour model; planning a cutting path based on the model and outputting initial parameters; and cutting according to the initial parameters and iteratively optimizing the path according to the feedback information until the cutting task is completed. The technical problems that in the semiconductor device manufacturing process, a traditional cutting mode is difficult to cope with dynamic interference of semiconductor materials, fine modeling and protection on the edges and the interiors of the machined parts are lacked, cutting precision is insufficient, and the machined parts are prone to being damaged and scrapped are solved, fine modeling on the edges and the interiors of the machined parts is achieved, and the cutting precision is improved. The cutting path is optimized by combining dynamic interference real-time feedback, the cutting precision is improved, the damage rejection rate of machined parts is reduced, and the technical effects of high precision and high reliability of semiconductor device manufacturing are met.

The invention relates to the technical field of semiconductor device manufacturing, solves the technical problem that in the prior art, automatic grain digging treatment cannot be carried out on detected LED support defective products, and provides a grain digging control method, device and equipment for LED support defective products. Acquiring a real-time image of the to-be-detected LED bracket under a preset target illumination condition; performing visual detection processing on the real-time image, and judging whether the to-be-detected LED bracket is a defective bracket product or not according to a visual detection processing result; when the to-be-detected LED bracket is judged to be a defective bracket product, defect position detection is carried out on the defective bracket product to obtain defect position information; according to the defect position information, defective stent particles in the defective stent products are removed, and particle digging control over the defective stent products is achieved. According to the automatic grain digging device, automatic grain digging treatment can be accurately carried out on the LED support defective products.

Embodiments of the present disclosure provide integrated circuit chips including via towers formed with stacks of conductive layers formed during fabrication of semiconductor devices and interconnect structures of the integrated circuit chips. The via towers may be connected to provide electrical power to subsequently stacked integrated circuit chips. The via towers according to the present disclosure reduce cost of fabrication because the via towers are fabricated without additional processing sequences. The via towers may be integrated in the circuit layout to form a low resistance power rail, therefore, improving performance.

Tin oxide film on a semiconductor substrate is etched selectively in a presence of photoresist by exposing the substrate to at least one of hydrogen-based chemistry and chlorine-based chemistry. In some implementations, a method of processing a semiconductor substrate starts by providing a semiconductor substrate having a patterned photoresist layer overlying a tin oxide layer. Next, openings are etched in the tin oxide layer using the patterned photoresist layer as a mask, and using at least one of a hydrogen-based etch chemistry and a chlorine-based etch chemistry. After the openings have been etched in the tin oxide layer, the photoresist layer is removed using an oxygen-based etch chemistry.

A method includes providing a first channel layer of a first transistor and a second channel layer of a second transistor over a substrate, forming a dipole layer over the first channel layer and the second channel layer, forming a patterned hard mask covering the second channel layer and exposing the first channel layer, removing the dipole layer from the first channel layer, removing the patterned hard mask, performing a thermal drive-in process, forming an interfacial dielectric layer on the first channel layer and the dipole layer, and forming a high-k dielectric layer on the interfacial dielectric layer. The dipole layer includes a p-dipole material.

The invention relates to the field of semiconductor device preparation, and provides a method for preparing a resistive layer of a variable resistance type memory based on laser pulse, which comprises the following steps: depositing a buffer layer on a bottom electrode layer of a pre-prepared variable resistance type memory, the material of the buffer layer comprising any one or more of tungsten, tantalum, nitrogen and boron; depositing a seed layer on the buffer layer; a target material is shot based on laser pulse shock, the target material is deposited on the seed layer to form a resistive layer, and the target material comprises any one or more of scandium, titanium, strontium, yttrium, lanthanum and barium and aluminum nitride. The method and the device are used for solving the defect of low read-write speed of the variable resistance type memory in the related technology, and the read-write speed of the variable resistance type memory can be improved based on preparation of the resistive layer by using aluminum nitride.

A semiconductor structure including a semiconductor channel member, a first dielectric layer over the semiconductor channel member, a second dielectric layer over the first dielectric layer, a metal layer over the second dielectric layer, first dipole elements distributed between the semiconductor channel member and the first dielectric layer, and second dipole elements distributed in the second dielectric layer.

The invention relates to a p-type niobium oxide dipole-based metal-oxide-semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductor device manufacturing. According to the technical scheme, the MOS device is provided. A gate dielectric stack of the MOS device sequentially comprises an interface layer, a high-k dielectric layer and a p-type electric dipole layer containing niobium oxide from bottom to top. According to the preparation method, the dipole layer is deposited by adopting an atomic layer deposition process, and then atoms in the dipole layer are driven to be diffused to the interface of the high-k dielectric layer and the interface layer through high-temperature rapid annealing treatment so as to form effective electric dipoles. Compared with the prior art, the high dielectric constant characteristic is utilized, the threshold voltage can be positively regulated and controlled to a larger extent, meanwhile, the increase of EOT is remarkably inhibited, and good interface quality is kept.

The invention provides a photoresist removing method and a semiconductor device manufacturing method, when photoresist on a substrate needs to be removed, corresponding oxygen-free gas is introduced into a plasma processing chamber and plasma excitation is carried out, so that corresponding rays are generated and act on the surface of the photoresist, the surface of the photoresist is re-melted, and the photoresist on the substrate is removed; according to the method, the photoresist is cleaned by the wet method, and then the hard shell on the surface of the photoresist is removed, so that the photoresist removal capability of subsequent wet cleaning can be effectively improved, the wet cleaning time is shortened, the photoresist is effectively removed, meanwhile, residues generated after the photoresist is removed by wet cleaning can be effectively avoided, the product yield is further improved, and the general applicability is high. Moreover, the surface of the photoresist is re-melted by mainly utilizing the action of rays generated after plasma excitation is carried out on the oxygen-free gas to remove the hard shell on the surface of the photoresist, so that the problem of secondary influence on the exposed substrate caused by the existing dry photoresist removing processes such as a plasma ashing process and the like can be effectively avoided.

A virtual fabrication environment for semiconductor device fabrication that includes an analytics module for performing process window optimization is discussed.

The invention provides high-temperature-resistant indium tin oxide (ITO) conductive glass and a preparation method thereof, and relates to the field of transparent conductive materials.The preparation method of the ITO conductive glass comprises the steps that firstly, a glass substrate is cleaned, and the clean glass substrate is placed on a magnetron sputtering preparation table; meanwhile, an ITO ceramic target material, a SnO2 ceramic target material and a Si3N4 ceramic target material are installed on different fixed targets of magnetron sputtering equipment respectively, then a bottom layer SnO2 thin film, an ITO thin film, a middle SnO2 thin film, a Si3N4 thin film and a top layer SnO2 thin film are sequentially deposited on the glass substrate through the magnetron sputtering technology, and a SnO2 / ITO / SnO2 / Si3N4 / SnO2 composite thin film structure is formed on the surface of the glass substrate; the conductive glass prepared by the method disclosed by the invention can still keep stable electrical properties and relatively high light transmittance in a high-temperature environment, meets the strict requirements on materials in the fields of semiconductor device manufacturing, solar cells and the like, and promotes the development of related industries.

There is provided a technique that includes a reaction container configured to process a substrate; a cleaning gas supply system configured to supply a cleaning gas into the reaction container; a lid configured to be capable of closing an opening of the reaction container and made of a metallic material; a protector installed over a surface of the lid at a side facing an inside of the reaction container and including a surface composed of a first non-metallic material; an internal space formed between surfaces of the lid and the protector facing each other; and an inert gas supply system configured to supply an inert gas to the internal space in a state in which the opening is closed by the lid.

The invention relates to a semiconductor device manufacturing technology, and aims to provide a preparation method of refined coke powder and high-purity isostatic pressing graphite. The method comprises the following steps: by taking calcined petroleum coke or calcined pitch coke as a raw material, crushing and grinding to obtain primary coke powder, then carrying out high-temperature halogen impurity removal treatment in a continuous heating manner, and introducing Freon gas in the process; cooling to obtain impurity-removed coke powder; and carrying out dispersion, grinding, shaping treatment, airflow classification and magnetic separation to obtain refined coke powder. According to the method, the impurity content is greatly reduced from the raw material end, the situation that a large number of metal impurities generated during smashing and grinding treatment cannot be eliminated in the graphitization process due to the fact that the metal impurities are located below the surface layer of a blank can be avoided, and the internal impurity content of a final graphite product is smaller than 20 ppm; higher tap density can be obtained, and a better mixing and kneading effect is realized; the porosity of an isostatic pressing graphite product can be reduced, the microstructure of a graphite material is effectively improved, and the corrosion resistance of the graphite material is effectively improved.

The invention discloses a process method for forming a cavity structure on a substrate, and the method comprises the following steps: providing a silicon substrate, the surface of the silicon substrate is provided with a mask layer, the mask layer is provided with a plurality of opening patterns, and the bottoms of the opening patterns are exposed out of the top surface of the silicon substrate; introducing a first etching gas to ignite the plasma, and etching the silicon substrate downwards according to the opening pattern to form a plurality of shallow trenches; forming a protective layer on the side wall of the shallow trench; introducing a second etching gas to ignite the plasma, and continuing to execute the vertical etching step downwards along the shallow trench to a preset depth so as to form a deep trench; and third etching gas is introduced to ignite the plasma, and the transverse etching step continues to be executed in the lateral direction along the lower portions of the deep grooves so that the multiple deep grooves can be communicated to form a cavity with a connecting bridge at the upper end. The method solves the problem that a cavity structure with a connecting bridge at the upper end is difficult to obtain on the substrate by a traditional semiconductor device manufacturing process.

The invention relates to the technical field of semiconductor device manufacturing, in particular to an etching method for improving the steepness of a graphic structure and a grating master mask, and the etching method comprises the following steps: S1, forming a graphic photoresist layer on the surface of a substrate; s2, the patterned photoresist layer is used as a masking layer, and the substrate is etched; wherein etching gas adopted in the etching process comprises SF6, Ar and CF4, the flow ratio of the SF6 to the Ar to the CF4 is (1-4): (1.5-4): 1, the radio frequency power of the etching process is 150-400 W, and the cavity pressure is 5-20 mTorr; and S3, the patterned photoresist layer is removed, and the patterned substrate is obtained. According to the method, the fluorocarbon polymer is generated in the etching process to protect the side wall, the vertical etching effect is completed while the morphology of the side wall is protected, the steepness of the side wall can reach 85-90 degrees, the etching steepness is greatly improved, the etching quality of a high-resolution pattern is improved, and a high-precision pattern structure is obtained.

The present disclosure provides a method for manufacturing a semiconductor device using selective vapor deposition and selective desorption. The method for manufacturing a semiconductor device includes providing a first layer having a first surface, and forming a second layer on the first layer such that a portion of the first surface is not covered by the second layer. The second layer has a second surface that meets the first surface. An inhibitor layer is formed on the first surface and the second surface, and the inhibitor layer on the second surface is selectively removed to expose the second surface. An interest layer is formed on the second surface. Physical properties of the first layer are different from physical properties of the second layer.

It is possible to economically and safely operate an apparatus by allowing wafers made of different materials to be accommodated together. There is provided a technique that includes: a mapping apparatus configured to determine a material of a substrate accommodated in a carrier and loaded into the substrate processing apparatus; and a controller configured to be capable of updating and holding first information on the material of the substrate loaded into the substrate processing apparatus, and capable of controlling the substrate processing apparatus to take out the carrier accommodating the substrate when the first information on the material of the substrate does not satisfy a predetermined condition specified for a current operation mode among conditions specified respectively for a plurality of operation modes.

Disclosed is a three-stage alignment system and alignment method for semiconductor lithography, which significantly improves the accuracy of wafer alignment in semiconductor manufacturing. The alignment system includes a first alignment module for coarse alignment with a relatively large tolerance range; a second alignment module equipped with a dual-camera system for intermediate refinement of alignment based on wafer marks; and a third alignment module for fine alignment within a submicron tolerance range using mask marks on a photomask. A robotic arm transfers the wafer between stages, maintaining the integrity of the alignment. The wafer alignment marks are cross-shaped, while the photomask marks are square, thereby ensuring precise alignment in the third alignment module. This innovative method increases both the efficiency and accuracy of semiconductor device manufacturing.

A virtual fabrication environment for semiconductor device fabrication that includes an analytics module for performing key parameter identification, process model calibration and variability analysis is discussed.

The invention relates to the technical field of semiconductor device manufacturing, in particular to an LED chip passivation layer preparation method and structure based on PECVD multi-section deposition, and the method comprises the following steps: providing an LED chip substrate with a light-emitting structure and an electrode formed on the surface; a passivation layer is deposited on the substrate through a PECVD (Plasma Enhanced Chemical Vapor Deposition) process in three stages: in the first deposition stage, an interface bonding layer is deposited and formed under the process conditions of low radio frequency power, high reaction pressure and low silicon-nitrogen gas flow ratio; and in the second deposition stage, a stress buffer layer is deposited and formed on the interface bonding layer under the process conditions of medium radio frequency power, medium reaction pressure and medium silicon-nitrogen gas flow ratio. Through deposition under the conditions of low power, high pressure and rich nitrogen in the first stage, firm combination, mainly based on strong chemical bonding (such as Si-N-Ga), between a passivation layer and a bottom layer (such as GaN) is achieved, and the problems of film layering and blistering caused by a traditional process are fundamentally solved.

To provide a semiconductor device manufacturing apparatus and manufacturing method that stack a plurality of chips with high accuracy and high yield.SOLUTION: A manufacturing apparatus comprises a first stage 101 that supports a substrate 11, a second stage 102 that supports chips 12a to 12c so as to face the substrate, and a movable camera unit 103 that captures alignment markers of the substrate and the chips. At least one of the first stage and the second stage is movable, and the second stage performs alignment using a reference marker 21 or a chip marker 22a formed on the chip 12a, and a chip marker 22c formed on the chip 12c supported by the second stage, and thereafter stacks the chip 12c on the chips 12a and 12b. A depth of field of an objective lens included in the camera unit is equal to or less than a sum of a thickness of the chip 12b sandwiched between the chip marker 22a and the chip marker 22c, and a distance between the chip 12a and the chip 12c after the alignment.SELECTED DRAWING: Figure 4

A substrate processing apparatus includes a boat including plural slots to hold at least one substrate, a process furnace that processes the at least one substrate held in the boat, a boat elevator that raises and lowers the boat, a transfer device that transfers the at least one substrate between plural carriers where the at least one substrate is stored and the boat, and a controller capable of controlling the boat elevator and the transfer device, wherein the controller sets plural positions where the transfer device transfers the at least one substrate to the boat elevator, and select the positions to minimize a number of shifts among the positions of the boat elevator or total time taken during the shifts.

The invention relates to the technical field of semiconductor device manufacturing, in particular to an FRD process control method with the characteristic that forward conduction voltage drop is positive temperature, and the method comprises the following steps: S1, ring base region process, S2, cut-off ring process, S3, Control process, S4, PT sputtering, S5, Pt kill, S6, metallization, S7, irradiation treatment, S8, back thinning, and S9, back gold process. In particular, through comprehensive application of the implantation dosage of boron ions, the diffusion condition of a platinum layer and electron irradiation, the method can ensure that the FRD has optimized performance that the forward conduction voltage drop is approximate to zero temperature or the positive temperature characteristic; and the forward conduction voltage drop can be kept in a relatively stable range and can also be improved along with the temperature rise, so that the current conduction capability and the thermal stability of the parallel device are improved.

The invention provides a wafer processing optimization method, a wafer processing optimization device and a semiconductor device, and belongs to the technical field of semiconductor device manufacturing. According to the wafer processing optimization method, the energy and the rotating speed of target ions are reasonably adjusted, matching is performed according to the type and the thickness of photoresist, the phenomenon that the photoresist is broken or falls off due to excessive bombardment of the ions is avoided, and the quality of the photoresist is improved. Therefore, the photoresist is kept stable in the ion implantation process, the surface of a wafer below is effectively protected, and a mask pattern in the photoetching process is prevented from being damaged, so that the subsequent photoetching process can be smoothly carried out, and the stability of the manufacturing process and the product quality are ensured.

A method of processing a substrate includes: providing a substrate having one or more mandrels comprising a mandrel material, wherein a layer of a spacer material coats horizontal surfaces and sidewalls of the one or more mandrels; and etching and completely removing the layer of the spacer material from the horizontal surfaces of the one or more mandrels and thereby exposing the mandrel material, without completely removing the spacer material residing at the sidewalls of the one or more mandrels. The etching includes exposing the substrate to a plasma formed using a mixture comprising a first gas and a polymer-forming gas, and wherein the etching comprises forming a polymer on the substrate. Polymer-forming gas may include carbon (C) and hydrogen (H).

A temperature regulating apparatus includes: a heating section configured to produce a heating liquid; a cooling section configured to produce a cooling liquid; a heating-liquid delivery pipe for delivering the heating liquid to the semiconductor-device manufacturing equipment; a cooling-liquid delivery pipe for delivering the cooling liquid to the semiconductor-device manufacturing equipment; a heating-side return pipe for returning a liquid mixture of the heating liquid and the cooling liquid that have passed through the semiconductor-device manufacturing equipment to the heating section; a cooling-side return pipe for returning the liquid mixture that has passed through the semiconductor-device manufacturing equipment to the cooling section; and at least one of a heating-side heat exchanger configured to exchange heat between the heating liquid and the liquid mixture and a cooling-side heat exchanger configured to exchange heat between the cooling liquid and the liquid mixture.

This semiconductor device manufacturing method comprises: a step for preparing a semiconductor module including a main substrate having a back surface that is exposed to the outside; and a step for bonding a main surface of a heat dissipation member and the back surface by diffusion bonding. The step for bonding by diffusion bonding of the manufacturing method includes a process for heating the main surface and the back surface from room temperature to a first temperature range. The manufacturing method comprises, after the step for preparing the semiconductor module and before the step for bonding by diffusion bonding: a step for heating the semiconductor module from room temperature to the first temperature range; and a step for flattening the back surface of the semiconductor module heated to the first temperature range.

This apparatus for manufacturing a GaAs semiconductor device comprises: a first metal layer forming unit for forming a first metal layer 161 on a GaAs semiconductor structure 11 including a GaAs semiconductor as a Group III-V compound semiconductor containing gallium (Ga) as a Group III element and arsenic (As) as a Group V element; a laser beam irradiation unit for irradiating the first metal layer 161 with a laser beam in order to create an ohmic contact between the GaAs semiconductor structure 11 and the first metal layer 161; and a second metal layer forming unit for forming, on the first metal layer 161, a second metal layer 162 having a higher laser beam reflectance than the first metal layer 161 after irradiation with the laser beam.

To provide a prober capable of accurately and stably bringing a probe needle into contact with a semiconductor chip without measuring a temperature.SOLUTION: A prober 100 generates first tip position data of a probe needle 121 at a predetermined time interval during a successive inspection of a semiconductor chip for constructing a transition pattern DB and further generates transition pattern data by arraying the generated first tip position data in time series. The prober 100 generates a transition pattern data group obtained by changing a preset temperature of a wafer chuck for each of transition pattern data. While semiconductor chips are newly successively inspected, the prober 100 then identifies, from a transition pattern data group, transition pattern data including a portion most similar to sub transition data, which are obtained by arraying second tip position data of the probe needle 121 in every predetermined timing in time series, and corrects a relative position based on the identified transition pattern data.SELECTED DRAWING: Figure 7