784 results about "Semiconductor device fabrication" patented technology

The invention relates to the technical field of semiconductor device manufacturing, solves the technical problem that in the prior art, automatic grain digging treatment cannot be carried out on detected LED support defective products, and provides a grain digging control method, device and equipment for LED support defective products. Acquiring a real-time image of the to-be-detected LED bracket under a preset target illumination condition; performing visual detection processing on the real-time image, and judging whether the to-be-detected LED bracket is a defective bracket product or not according to a visual detection processing result; when the to-be-detected LED bracket is judged to be a defective bracket product, defect position detection is carried out on the defective bracket product to obtain defect position information; according to the defect position information, defective stent particles in the defective stent products are removed, and particle digging control over the defective stent products is achieved. According to the automatic grain digging device, automatic grain digging treatment can be accurately carried out on the LED support defective products.

Embodiments of the present disclosure provide integrated circuit chips including via towers formed with stacks of conductive layers formed during fabrication of semiconductor devices and interconnect structures of the integrated circuit chips. The via towers may be connected to provide electrical power to subsequently stacked integrated circuit chips. The via towers according to the present disclosure reduce cost of fabrication because the via towers are fabricated without additional processing sequences. The via towers may be integrated in the circuit layout to form a low resistance power rail, therefore, improving performance.

A semiconductor structure including a semiconductor channel member, a first dielectric layer over the semiconductor channel member, a second dielectric layer over the first dielectric layer, a metal layer over the second dielectric layer, first dipole elements distributed between the semiconductor channel member and the first dielectric layer, and second dipole elements distributed in the second dielectric layer.

The invention relates to a p-type niobium oxide dipole-based metal-oxide-semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductor device manufacturing. According to the technical scheme, the MOS device is provided. A gate dielectric stack of the MOS device sequentially comprises an interface layer, a high-k dielectric layer and a p-type electric dipole layer containing niobium oxide from bottom to top. According to the preparation method, the dipole layer is deposited by adopting an atomic layer deposition process, and then atoms in the dipole layer are driven to be diffused to the interface of the high-k dielectric layer and the interface layer through high-temperature rapid annealing treatment so as to form effective electric dipoles. Compared with the prior art, the high dielectric constant characteristic is utilized, the threshold voltage can be positively regulated and controlled to a larger extent, meanwhile, the increase of EOT is remarkably inhibited, and good interface quality is kept.

A virtual fabrication environment for semiconductor device fabrication that includes an analytics module for performing process window optimization is discussed.

There is provided a technique that includes a reaction container configured to process a substrate; a cleaning gas supply system configured to supply a cleaning gas into the reaction container; a lid configured to be capable of closing an opening of the reaction container and made of a metallic material; a protector installed over a surface of the lid at a side facing an inside of the reaction container and including a surface composed of a first non-metallic material; an internal space formed between surfaces of the lid and the protector facing each other; and an inert gas supply system configured to supply an inert gas to the internal space in a state in which the opening is closed by the lid.

The invention relates to a semiconductor device manufacturing technology, and aims to provide a preparation method of refined coke powder and high-purity isostatic pressing graphite. The method comprises the following steps: by taking calcined petroleum coke or calcined pitch coke as a raw material, crushing and grinding to obtain primary coke powder, then carrying out high-temperature halogen impurity removal treatment in a continuous heating manner, and introducing Freon gas in the process; cooling to obtain impurity-removed coke powder; and carrying out dispersion, grinding, shaping treatment, airflow classification and magnetic separation to obtain refined coke powder. According to the method, the impurity content is greatly reduced from the raw material end, the situation that a large number of metal impurities generated during smashing and grinding treatment cannot be eliminated in the graphitization process due to the fact that the metal impurities are located below the surface layer of a blank can be avoided, and the internal impurity content of a final graphite product is smaller than 20 ppm; higher tap density can be obtained, and a better mixing and kneading effect is realized; the porosity of an isostatic pressing graphite product can be reduced, the microstructure of a graphite material is effectively improved, and the corrosion resistance of the graphite material is effectively improved.

The invention relates to the technical field of semiconductor device manufacturing, in particular to an etching method for improving the steepness of a graphic structure and a grating master mask, and the etching method comprises the following steps: S1, forming a graphic photoresist layer on the surface of a substrate; s2, the patterned photoresist layer is used as a masking layer, and the substrate is etched; wherein etching gas adopted in the etching process comprises SF6, Ar and CF4, the flow ratio of the SF6 to the Ar to the CF4 is (1-4): (1.5-4): 1, the radio frequency power of the etching process is 150-400 W, and the cavity pressure is 5-20 mTorr; and S3, the patterned photoresist layer is removed, and the patterned substrate is obtained. According to the method, the fluorocarbon polymer is generated in the etching process to protect the side wall, the vertical etching effect is completed while the morphology of the side wall is protected, the steepness of the side wall can reach 85-90 degrees, the etching steepness is greatly improved, the etching quality of a high-resolution pattern is improved, and a high-precision pattern structure is obtained.

The present disclosure provides a method for manufacturing a semiconductor device using selective vapor deposition and selective desorption. The method for manufacturing a semiconductor device includes providing a first layer having a first surface, and forming a second layer on the first layer such that a portion of the first surface is not covered by the second layer. The second layer has a second surface that meets the first surface. An inhibitor layer is formed on the first surface and the second surface, and the inhibitor layer on the second surface is selectively removed to expose the second surface. An interest layer is formed on the second surface. Physical properties of the first layer are different from physical properties of the second layer.

It is possible to economically and safely operate an apparatus by allowing wafers made of different materials to be accommodated together. There is provided a technique that includes: a mapping apparatus configured to determine a material of a substrate accommodated in a carrier and loaded into the substrate processing apparatus; and a controller configured to be capable of updating and holding first information on the material of the substrate loaded into the substrate processing apparatus, and capable of controlling the substrate processing apparatus to take out the carrier accommodating the substrate when the first information on the material of the substrate does not satisfy a predetermined condition specified for a current operation mode among conditions specified respectively for a plurality of operation modes.

A virtual fabrication environment for semiconductor device fabrication that includes an analytics module for performing key parameter identification, process model calibration and variability analysis is discussed.

The invention relates to the technical field of semiconductor device manufacturing, in particular to an LED chip passivation layer preparation method and structure based on PECVD multi-section deposition, and the method comprises the following steps: providing an LED chip substrate with a light-emitting structure and an electrode formed on the surface; a passivation layer is deposited on the substrate through a PECVD (Plasma Enhanced Chemical Vapor Deposition) process in three stages: in the first deposition stage, an interface bonding layer is deposited and formed under the process conditions of low radio frequency power, high reaction pressure and low silicon-nitrogen gas flow ratio; and in the second deposition stage, a stress buffer layer is deposited and formed on the interface bonding layer under the process conditions of medium radio frequency power, medium reaction pressure and medium silicon-nitrogen gas flow ratio. Through deposition under the conditions of low power, high pressure and rich nitrogen in the first stage, firm combination, mainly based on strong chemical bonding (such as Si-N-Ga), between a passivation layer and a bottom layer (such as GaN) is achieved, and the problems of film layering and blistering caused by a traditional process are fundamentally solved.

To provide a semiconductor device manufacturing apparatus and manufacturing method that stack a plurality of chips with high accuracy and high yield.SOLUTION: A manufacturing apparatus comprises a first stage 101 that supports a substrate 11, a second stage 102 that supports chips 12a to 12c so as to face the substrate, and a movable camera unit 103 that captures alignment markers of the substrate and the chips. At least one of the first stage and the second stage is movable, and the second stage performs alignment using a reference marker 21 or a chip marker 22a formed on the chip 12a, and a chip marker 22c formed on the chip 12c supported by the second stage, and thereafter stacks the chip 12c on the chips 12a and 12b. A depth of field of an objective lens included in the camera unit is equal to or less than a sum of a thickness of the chip 12b sandwiched between the chip marker 22a and the chip marker 22c, and a distance between the chip 12a and the chip 12c after the alignment.SELECTED DRAWING: Figure 4

A substrate processing apparatus includes a boat including plural slots to hold at least one substrate, a process furnace that processes the at least one substrate held in the boat, a boat elevator that raises and lowers the boat, a transfer device that transfers the at least one substrate between plural carriers where the at least one substrate is stored and the boat, and a controller capable of controlling the boat elevator and the transfer device, wherein the controller sets plural positions where the transfer device transfers the at least one substrate to the boat elevator, and select the positions to minimize a number of shifts among the positions of the boat elevator or total time taken during the shifts.

A method of processing a substrate includes: providing a substrate having one or more mandrels comprising a mandrel material, wherein a layer of a spacer material coats horizontal surfaces and sidewalls of the one or more mandrels; and etching and completely removing the layer of the spacer material from the horizontal surfaces of the one or more mandrels and thereby exposing the mandrel material, without completely removing the spacer material residing at the sidewalls of the one or more mandrels. The etching includes exposing the substrate to a plasma formed using a mixture comprising a first gas and a polymer-forming gas, and wherein the etching comprises forming a polymer on the substrate. Polymer-forming gas may include carbon (C) and hydrogen (H).

A temperature regulating apparatus includes: a heating section configured to produce a heating liquid; a cooling section configured to produce a cooling liquid; a heating-liquid delivery pipe for delivering the heating liquid to the semiconductor-device manufacturing equipment; a cooling-liquid delivery pipe for delivering the cooling liquid to the semiconductor-device manufacturing equipment; a heating-side return pipe for returning a liquid mixture of the heating liquid and the cooling liquid that have passed through the semiconductor-device manufacturing equipment to the heating section; a cooling-side return pipe for returning the liquid mixture that has passed through the semiconductor-device manufacturing equipment to the cooling section; and at least one of a heating-side heat exchanger configured to exchange heat between the heating liquid and the liquid mixture and a cooling-side heat exchanger configured to exchange heat between the cooling liquid and the liquid mixture.

This semiconductor device manufacturing method comprises: a step for preparing a semiconductor module including a main substrate having a back surface that is exposed to the outside; and a step for bonding a main surface of a heat dissipation member and the back surface by diffusion bonding. The step for bonding by diffusion bonding of the manufacturing method includes a process for heating the main surface and the back surface from room temperature to a first temperature range. The manufacturing method comprises, after the step for preparing the semiconductor module and before the step for bonding by diffusion bonding: a step for heating the semiconductor module from room temperature to the first temperature range; and a step for flattening the back surface of the semiconductor module heated to the first temperature range.

This apparatus for manufacturing a GaAs semiconductor device comprises: a first metal layer forming unit for forming a first metal layer 161 on a GaAs semiconductor structure 11 including a GaAs semiconductor as a Group III-V compound semiconductor containing gallium (Ga) as a Group III element and arsenic (As) as a Group V element; a laser beam irradiation unit for irradiating the first metal layer 161 with a laser beam in order to create an ohmic contact between the GaAs semiconductor structure 11 and the first metal layer 161; and a second metal layer forming unit for forming, on the first metal layer 161, a second metal layer 162 having a higher laser beam reflectance than the first metal layer 161 after irradiation with the laser beam.

To provide a prober capable of accurately and stably bringing a probe needle into contact with a semiconductor chip without measuring a temperature.SOLUTION: A prober 100 generates first tip position data of a probe needle 121 at a predetermined time interval during a successive inspection of a semiconductor chip for constructing a transition pattern DB and further generates transition pattern data by arraying the generated first tip position data in time series. The prober 100 generates a transition pattern data group obtained by changing a preset temperature of a wafer chuck for each of transition pattern data. While semiconductor chips are newly successively inspected, the prober 100 then identifies, from a transition pattern data group, transition pattern data including a portion most similar to sub transition data, which are obtained by arraying second tip position data of the probe needle 121 in every predetermined timing in time series, and corrects a relative position based on the identified transition pattern data.SELECTED DRAWING: Figure 7

Provided is a technique with which it is possible to drive a moving body without waiting for a recognition result.　A mounting apparatus comprises: a moving body; a drive unit that drives the moving body; an imaging device that captures an image of a target position of the moving body; and a control unit that, in parallel with calculation of the target position based on the image that is captured by the imaging device, drives the moving body using the drive unit on the basis of a base target position, and always sets the base target position to a position in front of the calculated target position.

The present invention provides a processing solution for semiconductor devices that excels in suppressing defects, a method for processing substrates, and a method for manufacturing semiconductor devices. [Solution] The present invention provides a processing solution for semiconductor devices, a method for processing substrates, and a method for manufacturing semiconductor devices, all of which contain a quaternary ammonium hydroxide compound, a cyclic ether compound, and an alkyl ketone, wherein the total content of the cyclic ether compound and the alkyl ketone is 0.001 ppm or more and less than 5 ppm.

The invention provides an etching method, and the method comprises the steps: providing a semiconductor structure which is provided with an etching stop layer, an interlayer dielectric layer and a graphical hard mask layer from bottom to top, employing a photoetching technology, combining with the graphical hard mask layer to etch the interlayer dielectric layer, and forming a through hole which penetrates through the interlayer dielectric layer and exposes the etching stop layer, and subsequently, through a two-step ashing process, impurities in the hard mask layer, the structure surface and the etching cavity are removed under the condition that bias power is not applied, and then the bias power is applied to remove residual impurities in the through hole, so that the bombardment time and the damage to the etching stop layer are remarkably reduced, the damage to a lower layer contact material in the subsequent step is avoided, and the production efficiency is improved. According to the method, the process development window is expanded, the stability and reliability of the etching process are improved, and the requirement for manufacturing a high-performance semiconductor device is met.

The invention discloses a continuous synthesis method of a cobalt-based alkyne precursor based on micro-reaction reinforcement, which belongs to the technical field of advanced electronic material preparation, and comprises the following steps: pre-cooling an n-hexane solution of Co2 (CO) 8 to-30 DEG C; the method comprises the following steps: introducing an n-hexane solution of Co2 (CO) 8 and 3, 3-dimethyl-1-butyne into a stacked microreactor array under the protection of nitrogen to react, and collecting a product after the reaction is completed. According to the present invention, the micro-channel reaction system containing the passivation layer is constructed, the substitution reaction process is precisely regulated and controlled, and the in-situ detection technology is combined so as to achieve the directional synthesis and collection of the specific coordination structure; the obtained product has excellent thermal stability and vapor pressure characteristics, and can meet the requirements of advanced semiconductor device manufacturing on precursor materials.

There is provided a technique that includes a processor configured to be capable of executing a process recipe to process a substrate; and a pressure controller configured to be capable of controlling a pressure of a process chamber, in which the substrate is processed, by adjusting an opening degree of a pressure regulating valve provided to an exhaust line of the process chamber, wherein when controlling the pressure of the process chamber, the pressure controller adjusts the opening degree of the pressure regulating valve and outputs information of the opening degree, and wherein while receiving the information of the opening degree from the pressure controller and monitoring an open / close state of the pressure regulating valve, the processor is configured to, when the information of the opening degree is a preset value, be capable of determining whether or not opening / closing of the pressure regulating valve happens.

The embodiment of the utility model provides semiconductor device manufacturing equipment, and the equipment comprises an equipment main body which is internally provided with a reaction chamber for accommodating a wafer; a quartz tube, a quartz tray and a heating lamp tube are arranged in the reaction chamber; the quartz tube is positioned in the middle of the reaction chamber and extends from the front end to the rear end of the reaction chamber; the quartz tray is positioned in the quartz tube and is used for bearing a wafer; the heating lamp tube is arranged on the periphery of the quartz tube; an oxygen content detection device; a detection probe of the oxygen content detection device is inserted into the reaction chamber and is used for detecting the oxygen content of the reaction chamber. The semiconductor device manufacturing equipment is used for detecting the oxygen content of the reaction chamber, real-time detection of the oxygen content in the equipment is achieved, the oxygen leakage condition can be found in time, the product yield is improved, and the production cost is reduced.

A substrate processing method is provided. The substrate processing method comprises loading a substrate onto a substrate support inside a chamber, forming a plasma inside the chamber, providing a first DC pulse signal to an electromagnet that generates a magnetic field inside the chamber and processing the substrate with the plasma, wherein the first DC pulse signal is repeated at a first period including a first section and a second section subsequent to the first section, the first DC pulse signal has a first level during the first section, and the first DC pulse signal has a second level different from the first level during the second section.

To provide a technique capable of selectively processing a desired surface among inner surfaces of a recess formed in a substrate.SOLUTION: (a) providing a substrate having a first end and a second end, the first end defining at least a portion of an inner surface of a recess, the second end being different from the first end; and (b) exposing the substrate to a treatment solution comprising a liquid reactive with the first end and an additive that reduces the surface tension of the liquid, thereby selectively removing the first end relative to the second end.SELECTED DRAWING: Figure 4

To provide a method of manufacturing a semiconductor device capable of improving reliability.SOLUTION: The method includes forming a first mask 100C having a plurality of openings MO on an upper surface divided into a first region 100E and a second region M1, forming a second mask M1 that exposes a portion of the first mask 100C disposed in the first region M1 and covers a portion of the first mask 100E disposed in the second region M2, etching the substrate SUB in the first region M1 using the first mask and the second mask as a mask, removing the second mask, and etching the substrate SUB in the first region and the second region using the first mask as a mask. 100E M2 100C 100C M1 M2.SELECTED DRAWING: Figure 7

To provide a resist pattern forming composition and a method for producing a resist pattern using the same. A resist pattern forming composition is a high-performance material that can be used in a semiconductor device producing step of a nanotechnology process, for example, a step of producing a semiconductor device that controls liquid crystals, quantum dots, or OLED displays formed on a substrate.

The purpose of the present invention is to provide: an etching method with which anisotropic etching of silicon is possible even if a gas having a low GWP is used; a method for manufacturing a semiconductor device; and an etching apparatus. The present invention relates to an etching method for etching silicon at 40°C or lower with use of a plasma gas that is obtained by converting, into plasma, an etching gas composition that contains at least one gas selected from the group consisting of fluorine-containing interhalogens, F2, Cl2, Br2, and I2.