Tunneling field-effect transistor with composite-mechanism strip-type grid and preparation method of tunneling field-effect transistor

Abstract

The invention discloses a tunneling field-effect transistor with a composite-mechanism strip-type grid and a preparation method of the tunneling field-effect transistor and belongs to the field of logic devices and circuits of field-effect transistors in CMOS (Complementary Metal Oxide Semiconductor) ultra-large-scale integrated (ULSI) circuits. The tunneling field-effect transistor has the advantages that the energy band of surface channels under the grid can be improved by changing the shape of the grid and utilizing a depletion effect of PN nodes on the two sides of the strip-type grid, and the subthreshold characteristic of the device is improved; since a composite mechanism is introduced into double-doped source areas, an ON state current of the device is improved; due to an I-shaped design of an active area, body leakage currents, including a source-drain direct tunneling current and a punching current, between the two doped source areas to a doped drain area can be greatly inhibited, and a short-channel effect is inhibited, so that the device with small size can be applied.

Description

technical field [0001] The invention belongs to the field of field effect transistor logic devices and circuits in CMOS ultra large integrated circuits (ULSI), and in particular relates to a bar-shaped gate tunneling field effect transistor with a compound mechanism and a preparation method thereof. Background technique [0002] Driven by Moore's Law, the feature size of traditional MOSFETs continues to shrink, and has now entered the nanometer scale. Following this, negative effects such as the short-channel effect of the device have become more serious. The leakage-induced barrier reduction, band-band tunneling and other effects make the off-state leakage current of the device continuously increase. At the same time, the sub-threshold slope of the traditional MOSFET is limited by the thermoelectric potential and cannot be reduced synchronously with the shrinking of the device size, thus increasing device power consumption. The power consumption problem has become the most...

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Problems solved by technology

TFET has many excellent characteristics such as low leakage current, low subthreshold slope, low operating voltage, and low power consumption. However, due to the limitation of source junction tunneling probability and tunneling area, TFET faces the problem of small on-state current, far It is not as good as traditional MOSFET devices, which greatly limits the application of TFET devices

In addition, TFET devices with a steep subthreshold slope are also difficult to realize experimentally, because it is difficult to achieve a steep doping concentration gradient at the source junction so that the electric field at the tunnel junction is not large enough when the device is turned on. This causes the subthreshold slope of the TFET to degrade from the theoretical value

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