Tunneling field-effect transistor with composite-mechanism strip-type grid and preparation method of tunneling field-effect transistor

A tunneling field effect and transistor technology, which is applied in the manufacture of diodes, semiconductor devices, semiconductor/solid-state devices, etc., can solve the problems of TFET subthreshold slope degradation, limit the application of TFET devices, and the electric field at the tunnel junction is not large enough, etc., to achieve Effect of suppressing short channel effect, improving subthreshold slope, and suppressing bulk leakage current
CN103474464AActive Publication Date: 2013-12-25PEKING UNIV
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Patent Information

Authority / Receiving Office
CN ยท China
Patent Type
Applications(China)
Current Assignee / Owner
PEKING UNIV
Publication Date
2013-12-25

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Abstract

The invention discloses a tunneling field-effect transistor with a composite-mechanism strip-type grid and a preparation method of the tunneling field-effect transistor and belongs to the field of logic devices and circuits of field-effect transistors in CMOS (Complementary Metal Oxide Semiconductor) ultra-large-scale integrated (ULSI) circuits. The tunneling field-effect transistor has the advantages that the energy band of surface channels under the grid can be improved by changing the shape of the grid and utilizing a depletion effect of PN nodes on the two sides of the strip-type grid, and the subthreshold characteristic of the device is improved; since a composite mechanism is introduced into double-doped source areas, an ON state current of the device is improved; due to an I-shaped design of an active area, body leakage currents, including a source-drain direct tunneling current and a punching current, between the two doped source areas to a doped drain area can be greatly inhibited, and a short-channel effect is inhibited, so that the device with small size can be applied.
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Description

technical field

[0001] The invention belongs to the field of field effect transistor logic devices and circuits in CMOS ultra large integrated circuits (ULSI), and in particular relates to a bar-shaped gate tunneling field effect transistor with a compound mechanism and a preparation method thereof. Background technique

[0002] Driven by Moore's Law, the feature size of traditional MOSFETs continues to shrink, and has now entered the nanometer scale. Following this, negative effects such as the short-channel effect of the device have become more serious. The leakage-induced barrier reduction, band-band tunneling and other effects make the off-state leakage current of the device continuously increase. At the same time, the sub-threshold slope of the traditional MOSFET is limited by the thermoelectric potential and cannot be reduced synchronously with the shrinking of the device size, thus increasing device power consumption. The power consumption problem has become the most...

Claims

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