Non-junction field-effect transistor

A field effect transistor, junctionless technology, applied in semiconductor devices, electrical components, circuits, etc., can solve problems such as poor stability

Active Publication Date: 2017-08-18
PEKING UNIV SHENZHEN GRADUATE SCHOOL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The present application provides a junctionless field effect transistor to solve

Method used

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Examples

Experimental program
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Embodiment 1

[0041] Please refer to figure 1 , which is a schematic structural diagram of a junctionless field effect transistor provided by an embodiment of the present invention, as shown in figure 1 As shown, the junctionless field effect transistor includes a channel region 1 , a source region 3 , a drain region 4 , a gate electrode 6 , a source electrode 8 and a drain electrode 9 .

[0042] Wherein, the source region 3 and the drain region 4 are symmetrically arranged on both sides of the channel region 1, so that the carriers in the channel region 1 can flow from the source region 3 to the drain region 4 or from the drain region 4 to the source region 3. transport, and the arrangement direction of the source region 3 and the drain region 4 can be understood as the channel direction to indicate the transport direction of carriers; in an exemplary embodiment, the source region 3 and the channel region 1 can also be An extension region 2 is provided, and an extension region 2 may also ...

Embodiment 2

[0066] Please refer to Figure 5 , is a schematic structural diagram of a tri-gate junctionless field effect transistor provided by an embodiment of the present invention. Such as Figure 5 As shown, the junctionless field effect transistor includes a channel region 1, an extension region 2, a source region 3 and a drain region 4; wherein, the channel region 1, the extension region 2, the source region 3 and the drain region 4 each include a top surface and two side surfaces, and the channel region 1, the extension region 2, the source region 3 and the drain region 4 are all set on the substrate 12, the substrate 12 may be a silicon substrate or the like, which is not limited in the embodiment of the present invention; The gate dielectric layer 5 covers the top surface and all sides of the channel region 1, and the gate electrode 6 covers the gate dielectric layer 5 to form a triple-gate structure, thereby enhancing the control ability of the gate electrode 6 to the channel r...

Embodiment 3

[0069] Please refer to Image 6 , is a schematic diagram of the structure of a gate-all-around junctionless field effect transistor provided by an embodiment of the present invention, as shown in Image 6 As shown, the junctionless field effect transistor includes a channel region 1, an extension region 2, a source region 3 and a drain region 4; wherein, the channel region 1, the extension region 2, the source region 3 and the drain region 4 are all cylindrical structure; the gate dielectric layer 5 is arranged around the outer periphery of the channel region 1, and the gate electrode 6 is further arranged around the outer periphery of the gate dielectric layer 5 to form a gate-ring structure; the isolation dielectric layer 7 is arranged around the outer periphery of the extension region 2, Thereby realizing isolation between the source electrode 8 and the gate electrode 6, and between the drain electrode 9 and the gate electrode 6; the source dielectric layer 10 is arranged a...

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Abstract

The invention provides a non-junction field-effect transistor. The non-junction field-effect transistor includes a source region and a drain region, wherein the source region and the drain region are arranged at two sides of a channel region in a central symmetry manner; the channel region, the source region and the drain region are the same in the doping type and the doping concentration; the channel region is provided with a gate dielectric layer and a gate electrode which is arranged on the gate dielectric layer; the source region and the drain region are respectively provided with a source electrode dielectric layer, a source electrode, a source end side electrode, a drain electrode dielectric layer, a drain electrode and a drain end side electrode; isolating dielectric layers isolate the source electrode from the gate electrode; and the work functions of the source electrode and the drain electrode are the work functions which are determined according to the doping type so as to form a conductive carrier layer on the surface of the source region and the surface of the drain region. The non-junction field-effect transistor can accumulate the corresponding type of carriers on the source region and the drain region to perform current transportation by adjusting the metal work functions of the source electrode and the drain electrode. The structure of the non-junction field-effect transistor can restrain the influence of rough edge of a technological fluctuation line on the device performance, can maintain the current driving capability of a non-junction device, and can optimize the subthreshold feature of the non-junction device so as to improve the stability of device.

Description

technical field [0001] The present application relates to the technical field of semiconductor integrated circuit devices, in particular to a junctionless field effect transistor. Background technique [0002] In the integrated circuit industry, under the guidance of Moore's Law, the device size is getting smaller and smaller. However, with the continuous shrinking of the device size, the performance of the device is more and more affected by the effects of threshold voltage drift and leakage current increase. Therefore, a variety of new device structures have been proposed to improve the gate control ability to suppress short-channel and other defects. effect. However, with the further reduction of devices, especially after the device size is reduced to sub-10 nanometers in the next few years, the precision control of doping becomes extremely important and challenging; on the one hand, the control precision of the doping number of channel atoms needs to reach One bit to a...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/08H01L29/10H01L29/78
CPCH01L29/0657H01L29/0847H01L29/1079H01L29/78
Inventor 万文波楼海君肖颖林信南
Owner PEKING UNIV SHENZHEN GRADUATE SCHOOL
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