Method and corresponding device for restraining tunneling transistor from leaking current and method for manufacturing corresponding device

Abstract

The invention discloses a method and corresponding device for restraining a tunneling transistor from leaking a current and a method for manufacturing the corresponding device and belongs to the field of field effect transistors and currents in a ULSI of a CMOS. According to the method for restraining the tunneling transistor from leaking the current, an insulating layer is inserted between a source zone and a body zone below a tunnel junction, an insulating layer is not inserted in the portion, between the source zone and a tunnel, of the tunnel junction, so that the source zone and a drain zone in a small-size TFET device are effectively prevented from being directly tunneled and leaking the current, and meanwhile the slope of a subthreshold value can be effectively improved. The method for manufacturing the corresponding device is compatible with the existing CMOS technology.

Description

technical field [0001] The invention belongs to the field of field effect transistor logic devices and circuits in CMOS ultra large integrated circuits (ULSI), and in particular relates to a method for suppressing the leakage current of tunneling transistors, a corresponding device and a preparation method. Background technique [0002] Driven by Moore's Law, the feature size of traditional MOSFETs has been shrinking, and now it has entered the nanometer scale. As a result, the negative effects of short-channel effects on devices have become more serious. The leakage-induced barrier reduction, band-band tunneling and other effects make the off-state leakage current of the device continuously increase. At the same time, the sub-threshold slope of the traditional MOSFET is limited by the thermoelectric potential and cannot be reduced synchronously with the shrinking of the device size, thus increasing device power consumption. The power consumption problem has become the most...

AI Technical Summary

Problems solved by technology

TFET has many excellent characteristics such as low leakage current, low subthreshold slope, low operating voltage, and low power consumption. Limit the application of TFET devices

On the other hand, for small-sized TFETs, when the gate length is less than about 20nm, the direct band-band tunneling current from source to drain in the body region will increase sharply, which will seriously degrade the leakage current and subthreshold slope of the TFET device.

TFETs using ultra-thin body SOI substrates can suppress this short-channel effect to a certain extent, but due to the existence of the buried oxide layer under the thin silicon film, the heat dissipation problem will become the main problem, and the self-heating effect is serious, which affects the device characteristics. Film requirements also increase the process complexity of the device

Images