Field effect transistor, semiconductor device and method for manufacturing same

Abstract

A field effect transistor is provided. The field effect transistor includes a semiconductor region formed on a substrate, wherein the semiconductor region comprises an undoped channel region, a source region including a first dopant type, and a drain region including a second dopant type, and wherein the channel region is formed of a group III-V compound semiconductor material. The field effect transistor further includes a high-K gate formed on the channel region, wherein the high-K gate is configured to generate electron tunneling between the source region and the drain region when a gate voltage is applied, and wherein a first contact surface between the source region and the channel region and a second contact surface between the drain region and the channel region are inclined.

Description

technical field [0001] The invention relates to the technical field of TFET (Tunneling Field Effect Transistor, tunneling field effect transistor), in particular to a field effect transistor, a semiconductor device and a manufacturing method thereof. Background technique [0002] In the development of semiconductor VLSI, under the guidance of CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) device scaling down (Scaling), the density and performance follow Moore's Law to be sustained and systematized increase. However, when the semiconductor industry develops to the 45nm node or smaller, the power consumption and power consumption density of chips have gradually become a problem that needs to be solved urgently. The power supply voltage has maintained 5V as the standard for all levels of technology for a long time. Therefore, scaling down of external voltage sources (VDD-scaling) has increasingly become a bottleneck restricting the dev...

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