120results about How to "Increase the overlapping area" patented technology

To form a sufficiently large storage capacitor, a liquid crystal display device includes a liquid crystal display panel having a first substrate, a second substrate, and a liquid crystal held between the first substrate and the second substrate, the liquid crystal display panel having multiple pixels arranged in matrix. The first substrate has, in a transmissive display area provided in each of the pixels, a laminated structure containing a first transparent electrode, a first insulating film, a second transparent electrode, a second insulating film, and a third transparent electrode which are laminated in this order. The first transparent electrode and the second transparent electrode are electrically insulated from each other and together form a first storage capacitor through the first insulating film, and the second transparent electrode and the third transparent electrode are electrically insulated from each other and together form a second storage capacitor through the second insulating film.

A laser beam pattern mask includes at least one or more transmitting parts, each transmitting part having a central portion and a pair of edge portions provided to both sides of the central portion, each having a substantially triangular shape defined by a virtual boundary line between the central portion and the corresponding edge portion, an upper outside extending from an upper end of the boundary line at an acute angle, and a lower outside extending from a lower end of the boundary line at the acute angle to meet the upper outside at a rounded corner.

The invention discloses a split gate type flash memory which comprises a semiconductor substrate, a word line, two discrete storage bit units and oxidation layers, wherein the word line is located at the bottom surface of the semiconductor substrate; the two storage bit units are located at two sides of the word line; the oxidation layers are arranged between the two storage bit units and the word line; each storage bit unit comprises a first insulation layer which is located on the bottom surface of the semiconductor substrate, a floating gate which is located on the surface of the first insulation layer, a second insulation layer which is located on the surface of the floating gate, a control gate which is located on the surface of the second insulation layer and a side wall structure which covers the floating gate and the control gate; each floating gate comprises a first floating gate and a second floating gate; and the distance between each first floating gate and the word line is greater than the distance between each second floating gate and the word line. The distance between the first floating gates and the word line is greater than the distance in the prior art, so that the coupling capacitance between the floating gates and the word line is smaller than the capacitance in the prior art, the coupling capacitance between the word line and the floating gates is as small as possible and then the erasing efficiency and the read-write efficiency of the flash memory are improved.

A display apparatus with a touch detection function capable of improving accuracy is provided. The display apparatus includes: a pixel array having a plurality of pixels arranged in a matrix form; and a plurality of signal wires arranged in the pixel array. Here, when an externally-detecting object is detected, a plurality of coils having areas overlapping with each other are formed of a plurality of signal wires (drive electrodes) among the plurality of signal wires, and a magnetic field generated in the plurality of respective coils are superimposed in an overlapped area by supplying a drive signal to the plurality of coils.

A MEMS capacitive pressure sensor is provided. The pressure sensor includes a substrate having a first region and a second region, and a first dielectric layer formed on the substrate. The pressure sensor also includes a first electrode layer formed on the first dielectric layer, and a second dielectric layer having first openings formed on the first electrode layer. Further, the pressure sensor includes conductive sidewalls connecting with the first electrode layer formed on sidewalls of the first openings, and a second electrode layer with a portion formed on the second dielectric layer in the second region and the rest suspended over the conductive sidewalls in the first region. Further, the pressure sensor also includes a chamber between the conductive sidewalls and the second electrode layer; and a third dielectric layer formed on the second electrode layer exposing a portion of the second electrode layer in the first region.

A semiconductor device includes two floating gates, a control gate and a first dielectric layer. The floating gates are disposed on a semiconductor substrate. The control gate partially overlaps each of the floating gates, and a part of the control gate is disposed between the two floating gates. Furthermore, the first dielectric layer disposed between the two floating gates and the control gate has a fixed thickness.

The invention provides a semiconductor and a forming method thereof, wherein the forming method of the semiconductor device comprises the following steps that a semiconductor substrate is provided, and a first interlayer dielectric layer is formed on the surface of the semiconductor substrate; a second interlayer dielectric layer is formed on the surface of the first interlayer dielectric layer; meanwhile, second interlayer dielectric layers in a first region and a second region are etched, a first groove is formed in the second interlayer dielectric layer formed in the first region, a second groove is formed in the second interlayer dielectric layer formed in the second region, in addition, the first groove comprises a first trench and a plurality of first through holes positioned at the bottom of the first trench, and a bulge is formed between the adjacent through holes; a metal blocking layer, an insulation layer and a third metal layer are sequentially formed in the first region, the metal blocking layer covers the bottom and the side wall of the first groove, and the metal blocking layer also covers the side wall and the top of the bulges. The semiconductor method and the forming method have the advantages that the mutual connection structure is formed, meanwhile, an MIM capacitor is formed, the unit area capacitance is increased, and the chip area is saved.

A power transmission apparatus includes: an input shaft; a selectable one-way clutch; a housing case; a center support; a lubricating oil reservoir; and an oil passage. The oil passage extends through a pocket plate disposed between the lubricating oil reservoir and a selector plate. The selector plate includes a through-hole. The through-hole is located at a position where the through-hole is not lined up with the opening of the oil passage in a radial direction and a circumferential direction of the selector plate in a non-engagement state of the selectable one-way clutch, and also at a position where the through-hole is lined up with the opening of the oil passage in the radial direction and the circumferential direction of the selector plate in an engagement state of the selectable one-way clutch.

A stacked-gate flash memory cell is provided having step-shaped poly-gates with increased overlap area between them in order to increase the coupling ratio and hence the program speed of the cell. The floating gate is first formed with a step and the intergate dielectric is conformally shaped thereon followed by the forming of the control gate thereon. The increase in the-overlap area can be achieved by forming gates with multiply connected surfaces of different shapes.

Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device are provided. The method and structure include the following steps. A gate oxide layer, a first semiconductor layer, and an insulating layer are formed sequentially over a provided semiconductor substrate. An etching process is used to etch the insulating layer. A semiconductor spacer is then deposited and used as a self-aligned etching mask. After the self-aligned etching, the insulating layer is removed and an insulating stacked structure is deposited. Finally, a second semiconductor layer is deposited and etched to form the control gate region.

The invention discloses an internal recycle photoelectron-catalytic oxidation combined treatment device. According to the treatment device, a water inlet (2) is formed in the bottom of a treatment device cylinder (1) and is communicated with a circular water distributor (3); wastewater is uniformly distributed to the bottom of the device through the circular water distributor (3); a photoelectron-catalytic oxidation combined treatment system (4) is arranged above the circular water distributor (3); a sediment mud bucket (5) is arranged under the circular water distributor (3) and is communicated with a mud discharge hole (6); under the condition that a direct-current power supply is loaded to the photoelectron-catalytic oxidation combined treatment system (4), the wastewater is lifted to the top of the device from the bottom of a photoelectron-catalytic oxidation unit (7); part of the wastewater is discharged out from a water outlet (9) in the upper part of the device; another part of the wastewater is further circulated to the bottom of the photoelectron-catalytic oxidation unit (7) through a central partitioning cylinder (8) and is mixed with water, then circulation of the wastewater inside the photoelectron-catalytic oxidation combined treatment system (4) is achieved, mud dregs generated from reaction can be discharged out from the mud discharge hole (6) at regular time, and generated tail gases can be discharged out from a top tail gas treater (10).

The invention discloses a tenon-and-mortise structure mortarless prefabrication assembled wall body building block, which is integrally formed by a pair of first cuboid sub building blocks in opposite arrangement and second cuboid sub building blocks clamped between the first sub building blocks in a staggered way, wherein parts, not in contact with the first sub building blocks, of the second sub building blocks form L-shaped tenons; and the parts, in contact with the second sub building blocks, of the first sub building blocks form L-shaped mortises. The wall body building block provided by the invention can be fast dismounted and mounted, can be cyclically used, and has the advantages that the structure is simple; a wall body is firm; the efficacy is high; and the cost is low, and the like. The goal of fast building the wall surface in indoor and outdoor positions can be achieved. Compared with a conventional technical product, the tenon-and-mortise structure mortarless prefabrication assembled wall body building block has the advantages that 90 percent of work hours can be saved; 70 percent of cost can be reduced; the mounting and the dismounting are very convenient and fast; the tenon-and-mortise structure mortarless prefabrication assembled wall body building block can be repeatedly used for many times; construction waste is not generated during dismounting or mounting; great benefits are achieved on environment and economy; and obvious social benefits are achieved.

The present invention describes a self mode locking laser and a method for self mode locking a laser. The laser (1) comprises a resonator terminated by first (3) and second (4) mirrors and folded by a third mirror (5). The third mirror comprises a single distributed Bragg reflector (17) upon which is mounted a multilayer semiconductor gain medium (18) and which includes at least one quantum well layer and an optical Kerr lensing layer (22). Self mode locking may be achieved by configuring the laser resonator such that the lensing effect of the Kerr lensing layer acts to reduce an astigmatism deliberately introduced to the cavity mode. The self mode locking of the laser may be further enhanced by selecting the length of the resonator such that a round trip time of a cavity mode is matched with an upper-state lifetime of one or more semiconductor carriers located within the gain medium.

The present invention describes a self mode locking laser and a method for self mode locking a laser. The laser (1) comprises a resonator terminated by first (3) and second (4) mirrors and folded by a third mirror (5). The third mirror comprises a single distributed Bragg reflector (17) upon which is mounted a multilayer semiconductor gain medium (18) and which includes at least one quantum well layer and an optical Kerr lensing layer (22). Self mode locking may be achieved by configuring the laser resonator such that the lensing effect of the Kerr lensing layer acts to reduce an astigmatism deliberately introduced to the cavity mode. The self mode locking of the laser may be further enhanced by selecting the length of the resonator such that a round trip time of a cavity mode is matched with an upper-state lifetime of one or more semiconductor carriers located within the gain medium.

The invention relates to an infrared ranging and guiding method applied to a servo-actuated dolly. According to the method, a module erected by an infrared ranging sensor is used for detecting location information of a followed object in real time, thereby realizing guidance of a servo-actuated dolly by a moving object within a certain range. The method comprises the following steps that: (1), two infrared ranging sensors are arranged on the dolly to erect an infrared ranging sensor device; (2), a two-dimensional coordinate system is established between the dolly and a followed object, the sensors scan corresponding ranges at certain frequencies continuously, and initial position information of the followed object is record; (3), the dolly moves based on the changing location information to realize accurate determination of a moving location, a moving direction, and a moving speed of the followed object, so that the dolly moves by following the target at any time and avoids obstacles in front of the dolly. Therefore, an objective of accurate determination of a moving location, a moving direction, and a moving speed of a target object by a dolly is achieved; and thus the dolly moves by following the target at any time and avoids obstacles in front of the dolly.

A non-volatile memory cell having a symmetric cell structure is disclosed. The non-volatile memory cell includes a substrate, a tunnel oxide layer, two floating gates, a dielectric layer, a plurality of spacers, a control gate, and two split gates. The substrate has at least two sources and a drain that is located between the sources. The floating gates are formed on the tunneling oxide layer, and each of floating gates is located between each source and the drain. The dielectric layer is formed on the floating gates. The control gate is formed over the drain and is between the floating gates. The split gates are located adjacent to outward sidewalls of the floating gates, respectively. Therefore, each of the split gates is opposite to the control gate through each of the floating gates.

The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate structure, where the substrate structure includes: a substrate having a first device region and a second device region, a first dummy gate structure at the first device region, a second dummy gate structure at the second device region, and an LDD region below the first dummy gate structure. The first dummy gate structure includes a first dummy gate dielectric layer at the first device region, a first dummy gate on the first dummy gate dielectric layer, and a first spacer layer at a side wall of the first dummy gate. The second dummy gate structure includes a second dummy gate dielectric layer at the second device region, a second dummy gate on the second dummy gate dielectric layer, and a second spacer layer at a side wall of the second dummy gate. The method further includes removing the first dummy gate; etching back the first spacer layer to reduce a thickness of the first spacer layer; removing an exposed portion of the first dummy gate dielectric layer to form a first trench; and removing the second dummy gate and exposed second dummy gate dielectric layer to form a second trench.