Low-power consumption tunneling field effect transistor (TFET) of fork-structure grid structure

Abstract

The invention provides a low-power consumption tunneling field effect transistor (TFET), belonging to the field of a field effect transistor logic device and a circuit of CMOS (complementary metal oxide semiconductors) ultra large scale integrated circuit (ULSI). The TFET provided by the invention comprises a source, a drain and a control grid, wherein the control grid extends towards a source electrode end into a fork structure, and the fork-structure control grid is composed of an extended grid region and an original control grid region; and the active region which is covered below the extended grid region is similarly a channel region and is made of a substrate material. According to the invention, the channel is enclosed by the source region of the TFET, and the conduction current of the device is improved; and compared with the existing panel TFET, the TFET has provided by the invention has the advantage that under the conditions of the same technology and the same active region size, higher conduction current and a steep subthreshold gradient can be obtained.

Description

technical field [0001] The invention belongs to the field of field effect transistor logic devices and circuits in CMOS ultra large integrated circuits (ULSI), in particular to a tunneling field effect transistor (TFET). Background technique [0002] As the size of devices continues to shrink, negative effects such as short-channel effects of devices are increasing. DIBL (drain-to-barrier lowering effect) and band-band tunneling effect make the off-state leakage current of the device continuously increase. Not only that, the subthreshold slope of traditional MOSFET devices cannot be reduced synchronously with the reduction of device size due to the theoretical limitation of KT / q. Therefore, as the threshold voltage of the device decreases, the subthreshold leakage current also increases continuously. Today, the resulting static power consumption has become the focus of everyone's attention in small-size devices. In order to break through the theoretical limit of conventio...

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Problems solved by technology

At present, the main challenge encountered by TFET is the insufficient driving current caused by the influence of tunneling.

At this stage, the main methods to improve the conduction current of TFET are: (1) Thinning the thickness of the gate dielectric layer, increasing the dielectric constant of the gate dielectric layer to improve the gate control ability, this method uses high K dielectric to grow silicon dioxide gate dielectric It is said that the process is relatively complicated, and due to the influence of gate leakage, the thickness of the dielectric layer also has a limit value; (2) use narrow bandgap semiconductor materials to reduce the width of the tunneling barrier and increase the tunneling current. This method is due to the introduction of other semiconductors Materials undoubtedly increase the cost and process complexity

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