A kind of preparation method of tunneling field effect transistor

Abstract

The present invention discloses a method for preparing a tunneling field effect transistor, belonging to the field of field effect transistor logic devices in a CMOS super-large-scale integration (ULSI) circuit. The tunneling field effect transistor of an ultra-steep source junction is realized through preparation process design. The device characteristic can be improved significantly, at the same time, the preparation method is compatible with standard CMOS IC technology, TFET devices can be effectively integrated in a CMOS integrated circuit, a low power consumption integrated circuit formed by TFET can be prepared by using standard process, the production cost is greatly reduced, and the process flow is simplified.

Description

technical field

[0001] The invention belongs to the field of CMOS ultra-large scale integrated circuit (ULSI) field-effect transistor logic devices, and in particular relates to a preparation method of a tunneling field-effect transistor realizing an ultra-steep source junction. Background technique

[0002] Since the birth of integrated circuits, microelectronics integration technology has been developing continuously in accordance with "Moore's Law", and the size of semiconductor devices has been continuously reduced. As semiconductor devices enter the deep submicron range, traditional MOSFET devices are limited by the conduction mechanism of self-diffusion drift, and the subthreshold slope is limited by the thermoelectric potential kT / q, which cannot be reduced synchronously with the reduction of device size. As a result, the reduction of leakage current of MOSFET devices cannot meet the requirements of device size reduction, the energy consumption of the entire chip cont...

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