Semiconductor structure and method for preparing the same

Abstract

The present disclosure provides a semiconductor structure including a substrate, a bottom gate portion disposed in the substrate, a top gate portion stacked over the bottom gate portion, a first channel layer sandwiched between the top gate portion and the bottom gate portion, and a source / drain region disposed in the substrate at two opposite sides of the top gate portion.

Description

PRIORITY DATA[0001]This patent claims the benefit of U.S. Provisional Patent Application Ser. No. 62 / 609,999 filed Dec. 22, 2017, the entire disclosure of which is hereby incorporated by reference.TECHNICAL FIELD[0002]The present disclosure relates to a semiconductor structure and a method for preparing the same, and more particularly, to a semiconductor structure for a memory device and a method for preparing the same.DISCUSSION OF THE BACKGROUND[0003]Electrical products are becoming lighter, thinner, shorter, and smaller, and DRAMs are being scaled down to match the trends of high integration and high density. A DRAM including many memory cells is one of the most popular volatile memory devices utilized today. Each memory cell includes a transistor and at least a capacitor, wherein the transistor and the capacitor form a series connection with each other. The memory cells are arranged into memory arrays. The memory cells are addressed via a word line and a digit line (or bit line)...

AI Technical Summary

Benefits of technology

[0026]In the present disclosure, a method for preparing the semiconductor structure is provided. By forming the bottom gate portion, the top gate portion and the channel layer sandwiched therebetween, a dual-channel region is formed under a single voltage during operation. Consequently, gate control ability is improved due to the dual gate portions. Further, Idsat is increased and Idoff is reduced due to the fully depleted channel layer. Further, since the channel layer is sandwiched between the bottom gate portion and the top gate portion, the bottom gate portion can be embedded more deeply in the substrate to reduce current leakage without increasing the channel length. Accordingly, subthreshold slope and on-off ratio are both increased.

[0027]In contrast, with a comparative semiconductor structure, the channel length is limited by the depth of the gate structure, and thus the semiconductor structure suffers from, lower Idsat and higher current leakage.

Problems solved by technology

Therefore, with the continuing reduction of the device size, it becomes an important issue to increase Idsat and reduce Idoff in order to achieve a smaller memory cell layout.

In contrast, with a comparative semiconductor structure, the channel length is limited by the depth of the gate structure, and thus the semiconductor structure suffers from, lower Idsat and higher current leakage.

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