Self-alignment preparation method of drain terminal negative overlapping region of tunneling transistor

Abstract

The invention discloses a self-alignment preparation method for a self-alignment gate-drain negative overlapping region of a tunneling field effect transistor, and belongs to the field of field effecttransistor logic devices and circuits in a CMOS ultra-large integrated circuit (ULSI). According to the method, asymmetric side wall structures are designed on the two sides of a tunneling transistorgate, the side, close to a source end, of the gate is a thin side wall, and the side, close to a drain end, of the gate is a thick side wall. According to the invention, by reasonably utilizing the thin side wall and the thick side wall in the standard CMOS process, the thin side wall at the source end is used as a hard mask for transistor source region injection, and the thick side wall at the drain end is used as a hard mask for transistor drain region injection, so that special materials and special processes are not introduced, the bipolar effect of a tunneling field effect transistor (TFET) is inhibited, the fluctuation characteristic of the device is optimized, it can be guaranteed that the TFET can be mixed and integrated with a standard CMOS device, and complex and diversified circuit functions are achieved.

Description

technical field [0001] The invention belongs to the field of field effect transistor logic devices and circuits in a CMOS ultra large integrated circuit (ULSI), and in particular relates to the design and preparation of a drain terminal negative overlap region of a tunneling transistor. Background technique [0002] With the continuous development of integrated circuits, the feature size of devices continues to decrease, and the power consumption density of chips continues to increase. Circuit power consumption has gradually become an important factor limiting the scaling down of integrated circuits. In order to reduce the power consumption of the circuit, a better way is to reduce the power supply voltage. However, the subthreshold slope of the MOSFET is limited by the thermoelectric potential, which cannot be lower than 60mV / dec at room temperature. In the case of maintaining a certain driving capability, further reducing the power supply voltage will lead to an exponentia...

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Problems solved by technology

However, this method will make the doping of the device heavily dependent on the lithography accuracy, and will introduce additional fluctuation sources, which is not conducive to the consistency of the device and affects the large-scale integration application of TFET devices.

And the use of this method is not conducive to the metal silicide treatment of the device, which affects the contact of the device, and is not conducive to the use of technologies such as impurity segregation

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