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FD-GOI tunneling field effect transistor with abrupt tunneling junction and manufacturing method

A technology of tunneling field effect and tunneling junction, which is applied in semiconductor/solid-state device manufacturing, diodes, semiconductor devices, etc., can solve the problems of subthreshold slope theoretical value degradation and small driving current, and achieve suppression of bipolar effect and parasitic Effect of low capacitance and reduced subthreshold slope

Inactive Publication Date: 2016-01-20
XIAN UNIV OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to overcome the problems of low driving current of existing silicon-based TFET devices and the degradation of subthreshold slope relative to the theoretical value, the present invention proposes a FD-GOI tunneling field effect transistor with abrupt tunneling junction and its preparation method

Method used

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  • FD-GOI tunneling field effect transistor with abrupt tunneling junction and manufacturing method
  • FD-GOI tunneling field effect transistor with abrupt tunneling junction and manufacturing method
  • FD-GOI tunneling field effect transistor with abrupt tunneling junction and manufacturing method

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Embodiment 1

[0055] See figure 1 , figure 1 It is a flowchart of a method for preparing an FD-GOI tunneling field effect transistor with a sudden tunnel junction according to an embodiment of the present invention, and the method includes the following steps:

[0056] Step (a), selecting a fully depleted germanium-on-insulator (Fully Depleted Germanium-On-Insulator, referred to as FD-GOI) substrate;

[0057] Step (b), forming shallow trench isolation on the FD-GOI substrate by an etching process;

[0058] Step (c), forming a drain region pattern by photolithography on the FD-GOI substrate, and forming a drain region by using an ion implantation process with glue;

[0059] Step (d), forming a source region pattern by photolithography on the FD-GOI substrate, and forming a source region trench by a dry etching process;

[0060] Step (e), depositing germanium material in the trench of the source region, and performing in-situ doping at the same time, forming a source region with a higher...

Embodiment 2

[0095] See Figure 2a-Figure 2h It is a schematic diagram of a method for preparing a FD-GOI tunneling field-effect transistor with a sudden tunnel junction according to an embodiment of the present invention; the specific steps are as follows:

[0096] (1) Select the FD-GOI substrate. Such as Figure 2a As shown, the FD-GOI substrate includes a top layer of germanium 101 , a buried oxide layer 102 such as a buried layer of silicon dioxide, and a bottom layer of silicon 103 .

[0097] The reason for using the FD-GOI substrate is that the Ge material has a small bandgap, high tunneling probability, high carrier mobility, and good velocity characteristics, which is conducive to improving the driving current of the tunneling field effect transistor; the GOI substrate formed Semiconductor devices have the advantages of low power consumption, high speed, high integration density, strong anti-interference ability, strong anti-irradiation ability, and simple process, which can prov...

Embodiment 3

[0127] See image 3 , image 3 It is a schematic flow chart of a method for preparing an FD-GOI tunneling field-effect transistor with an abrupt tunneling junction according to an embodiment of the present invention, to prepare an N-type FD-GOI tunneling field-effect transistor with an abrupt tunneling junction with a channel length of 45 nm. Taking the transistor as an example to describe in detail, the specific steps are as follows:

[0128] 1. Select FD-GOI substrate

[0129] The crystal orientation of the FD-GOI substrate can be (100) or (110) or (111), without any limitation here. In addition, the doping type of the FD-GOI substrate 101 can be N-type or It is P-type, and the doping concentration is, for example, 10 14 ~10 17 cm -3 , the thickness of the top Ge layer is, for example, 20-100 nm, preferably 20 nm.

[0130] 2. Shallow trench isolation formation

[0131] 2.1 Form the first protective layer on the FD-GOI substrate.

[0132] First, two layers of materials ...

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Abstract

The invention relates to an FD-GOI tunneling field effect transistor with an abrupt tunneling junction and a manufacturing method. The manufacturing method comprises: selecting an FD-GOI substrate; forming shallow trench isolation with an etching process; performing photoetching on the FD-GOI substrate to form a drain region graph and forming a drain region with an adhesive ion implantation process; step (d), performing photoetching on the FD-GOI substrate to form a source region graph and forming a source region trench with a dry etching process; step (e), depositing a germanium material in the source region trench and performing in-situ doping at the same time to form a source region with the doping concentration higher than that of the drain region; step (f), forming a gate interface layer, a gate medium layer and a normal gate layer on a top-layer germanium surface of the FD-GOI substrate, and performing etching to form a normal gate; forming a back gate layer on a bottom-layer silicon surface of the FD-GOI substrate, and performing etching to form a back gate; and step (g), photoetching lead windows, depositing metal, and photoetching leads to form metal leads of the source region, the drain region, the normal gate and the back gate, thereby finally forming the FD-GOI tunneling field effect transistor with the abrupt tunneling junction.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to an FD-GOI tunneling field effect transistor with an abrupt tunneling junction and a preparation method. Background technique [0002] Integrated Circuit (IC for short) technology follows the development of "Moore's Law" and has entered the nanoscale. Challenges from short channel effects, parasitic effects, and quantum tunneling make it increasingly difficult for traditional microelectronic device technology to meet the requirements of IC. The requirement of continuous technological development, especially the increasingly serious power consumption problem, has become the biggest bottleneck in continuing "Moore's Law". [0003] Tunneling Field Effect Transistor (Tunneling Field Effect Transistor, referred to as TFET) adopts the physical mechanism of band-band tunneling, so that its sub-threshold swing is not limited by the limit value KT / q of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/331H01L29/739H01L29/10
CPCH01L29/1079H01L29/66356H01L29/7391
Inventor 李妤晨徐大庆张岩秦学斌
Owner XIAN UNIV OF SCI & TECH
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