PNIN/NPIP type SSOI TFET with abrupt tunneling junctions and preparation method thereof

A technology of tunneling junction and dry etching, which is applied in semiconductor/solid-state device manufacturing, diodes, semiconductor devices, etc., can solve the problems of limiting the tunneling probability of TFET devices, reducing the average sub-threshold slope, and small driving current, etc., to achieve Effects of suppressing bipolar effects, increasing the probability of tunneling, and reducing the forbidden band width

Inactive Publication Date: 2016-01-13
XIAN UNIV OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there are not many experimental reports of traditional Si-based TFET devices breaking through 60mV / dec, and the subthreshold slope of TFET devices is still a function of gate voltage, and its value tends to deteriorate with the increase of gate voltage. The average subthreshold slope of is a hard problem
In addition, Si material is an indirect bandgap semiconductor, and the bandgap width is relatively large, which limits the tunneling probability of TFET devices. Therefore, compared with traditional MOSFET devices, the driving current of this device is smaller

Method used

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  • PNIN/NPIP type SSOI TFET with abrupt tunneling junctions and preparation method thereof
  • PNIN/NPIP type SSOI TFET with abrupt tunneling junctions and preparation method thereof
  • PNIN/NPIP type SSOI TFET with abrupt tunneling junctions and preparation method thereof

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Embodiment 1

[0026] See figure 1 , figure 1 It is a flow chart of a preparation method of a PNIN / NPIP type SSOITFET with a sudden tunnel junction according to an embodiment of the present invention, and the preparation method includes the following steps:

[0027] (a) preparing an SSOI substrate;

[0028] (b) forming shallow trench isolation on the SSOI substrate by using a dry etching process;

[0029] (c) Photolithographically forming a drain region pattern at a designated drain region position on the SSOI substrate, and performing ion implantation by an implantation process to form a drain region;

[0030] (d) using a dry etching process to form a source region trench at a designated source region position on the SSOI substrate;

[0031] (e) using an ion implantation process to implant ions obliquely at a certain angle to the sidewall of the trench in the source region, so as to form a thin doped region in the trench near the sidewall of the trench in the source region, and the thi...

Embodiment 2

[0076] See Figure 2a-2i , Figure 2a-Figure 2i It is a schematic diagram of a preparation method of a PNIN / NPIP type SSOITFET with an abrupt tunneling junction according to an embodiment of the present invention. Taking the preparation of a PNIN type SSOITFET with an abrupt tunneling junction with a channel length of 45 nm as an example, the specific steps are as follows:

[0077] 1. Prepare SSOI substrate, such as Figure 2a Shown:

[0078] 1.1 Epitaxial growth.

[0079] Using selective epitaxy technology, a graded SiGe layer is epitaxially grown on a Si wafer at a high temperature of 800°C to 900°C, and the gas phase precursor GeH is dynamically adjusted during the epitaxial growth process 4 and SiH 2 Cl 2 The flow rate ratio of the gradient SiGe layer is controlled to increase the Ge composition of the graded SiGe layer from 0 to the Ge composition of the relaxed SiGe layer of the fixed composition, and then a layer of fixed composition is epitaxially grown at a high ...

Embodiment 3

[0140] See image 3 , image 3 It is a structural schematic diagram of a PNIN / NPIP type SSOITFET with an abrupt tunnel junction according to an embodiment of the present invention. The PNIN / NPIP SSOITFET with an abrupt tunnel junction of the present invention includes a top strained Si layer, a buried oxide layer, a bottom Si layer, a gate Dielectric layer, front gate, back gate, highly doped source region, low doped drain region and N-type / P-type thin layer.

[0141] Specifically, the SSOI substrate is prepared by intelligent stripping technology, the Ge composition of the strain-inducing layer SiGe layer is preferably 0.4, the strained Si layer is directly located on the insulating layer, and there is no strain-inducing layer SiGe layer under it, and the thickness of the strained Si layer is preferably 10-20nm, the thickness is less than the critical thickness of strained Si when the Ge composition is 0.4, and the doping concentration is less than 10 17 cm -3 .

[0142] Sp...

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Abstract

The invention relates to a PNIN/NPIP type SSOI TFET with abrupt tunneling junctions and a preparation method thereof. The preparation method comprises the steps that an SSOI substrate is prepared; shallow trench isolation is formed; a drain region pattern is formed through photoetching, and adhesive ions are injected so that a drain region is formed; a source region trench is formed through dry etching; the ions are injected in the side wall of the source region trench at a certain inclined angle by adopting an ion injection technology, Si material is deposited in the source region trench, and in-situ doping is performed so that a source region is formed; a gate dielectric layer and a front gate layer are formed on the upper surface of the substrate, a front gate is formed through etching, a back gate layer is formed on the lower surface of the substrate, and a back gate is formed through etching; and a lead-wire window is photoetched, metal is deposited and a lead-wire is photoetched so that source/drain and front/back gate lead-wires are formed. Drive current of the TFET can be effectively enhanced and subthreshold slope of the TFET can be reduced.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a PNIN / NPIP type SSOITFET with an abrupt tunnel junction and a preparation method. Background technique [0002] Integrated Circuit (IC for short) technology follows the development of "Moore's Law" and has entered the nanoscale. Challenges from short channel effects, parasitic effects, and quantum tunneling make it increasingly difficult for traditional microelectronic device technology to meet the requirements of IC. The requirement of continuous technological development, especially the increasingly serious power consumption problem, has become the biggest bottleneck in continuing "Moore's Law". [0003] Tunneling Field Effect Transistor (Tunneling Field Effect Transistor, referred to as TFET) adopts the physical mechanism of band-band tunneling, so that its sub-threshold swing is not limited by the limit value KT / q of the traditional MOSF...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/66H01L21/762H01L29/739
CPCH01L21/76254H01L29/66356H01L29/7391
Inventor 李妤晨徐大庆秦学斌
Owner XIAN UNIV OF SCI & TECH
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