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Tensionally strained germanium tfet on pnin/npip type insulating layer with abrupt tunneling junction and preparation method

A technology of straining germanium on an insulating layer, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of small driving current, degradation of the theoretical value of subthreshold slope, and reduction of subthreshold slope, so as to suppress bipolar effect, the effect of increasing the driving current and switching speed, and improving the mobility

Inactive Publication Date: 2018-01-05
XIAN UNIV OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In order to overcome the problems of low driving current of the existing silicon-based TFET devices and the degradation of the subthreshold slope relative to the theoretical value, the present invention proposes a PNIN / NPIP type insulating layer tension-strained germanium TFET with abrupt tunneling junctions and a preparation method thereof, which can be used Effectively increase the driving current of TFET devices and reduce the subthreshold slope

Method used

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  • Tensionally strained germanium tfet on pnin/npip type insulating layer with abrupt tunneling junction and preparation method
  • Tensionally strained germanium tfet on pnin/npip type insulating layer with abrupt tunneling junction and preparation method
  • Tensionally strained germanium tfet on pnin/npip type insulating layer with abrupt tunneling junction and preparation method

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Embodiment 1

[0026] See figure 1 , figure 1 It is a flowchart of a method for preparing a tensile strained germanium TFET on a PNIN / NPIP type insulating layer with an abrupt tunnel junction according to an embodiment of the present invention, and the method includes the following steps:

[0027] (a) preparing a tensile-strained germanium substrate on an insulating layer; the substrate sequentially includes a bottom silicon layer, a buried oxide layer and a top tensile-strained germanium layer from bottom to top;

[0028] (b) forming shallow trench isolation on the substrate by an etching process;

[0029] (c) forming a drain region pattern on the upper surface of the substrate by a photolithography process and forming a drain region on the substrate by using an ion implantation process with glue;

[0030] (d) forming source region trenches on the substrate by a dry etching process;

[0031] (e) using an inclined ion implantation process to implant ions into the sidewall of the source ...

Embodiment 2

[0078] See Figure 2a-2i , Figure 2a-Figure 2i It is a schematic diagram of a preparation method of a PNIN / NPIP type insulating layer tensile strain germanium TFET with an abrupt tunneling junction according to an embodiment of the present invention, so as to prepare a PNIN type insulating layer tensile straining with a channel length of 45 nm. Germanium TFET is taken as an example to describe in detail, and the specific steps are as follows:

[0079] 1. Prepare a strained germanium substrate on an insulating layer. Such as Figure 2a , the tensile-strained germanium-on-insulator substrate includes a top layer of tensile-strained germanium 101 , a buried oxide layer 102 such as a buried layer of silicon dioxide, and a bottom layer of silicon 103 .

[0080] 1.1 Epitaxial growth.

[0081] Using molecular beam epitaxy (Molecular Beam Epitaxy, MBE) technology or metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD) technology, at the tempera...

Embodiment 3

[0143] See image 3 , image 3 It is a schematic structural diagram of a PNIN / NPIP tensile strained germanium TFET on an insulating layer with an abrupt tunneling junction according to an embodiment of the present invention. The PNIN / NPIP tensile strained germanium on an insulating layer TFET with an abrupt tunneling junction of the present invention includes a Deplete the top tensile strain germanium layer, buried oxide layer, bottom silicon layer, gate interface layer, gate dielectric layer, front gate, back gate, heavily doped source region, low doped drain region and N-type / P-type thin layer.

[0144] Specifically, the thickness of the fully depleted top tensile strained germanium layer can be selected from 20 to 30 nm, preferably 20 nm, and the doping concentration is less than 10 17 cm -3 .

[0145] Specifically, the gate interface layer is preferably yttrium oxide (Y 2 o 3 ) material, the high-K material layer can be selected from hafnium-based materials (a class of ...

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Abstract

The invention relates to a PNIN / NPIP type tensile strained germanium on insulator TFET with abrupt tunneling junctions and a preparation method thereof. The preparation method comprises the steps that a tensile strained germanium on insulator substrate is prepared; shallow trench isolation is formed by adopting an etching technology; a drain region pattern is formed on the upper surface of the substrate by adopting a photoetching technology and a drain region is formed by adopting an adhesive ion injection technology; a source region trench is formed on the substrate by adopting the etching technology; ions are injected in the side wall of the source region trench close to a channel region by adopting an inclined ion injection technology so that a thin layer doped region is formed; germanium material is deposited in the source region trench and in-situ doping is performed so that a source region is formed; a gate interface layer, a gate dielectric layer and a front gate layer are formed on the upper surface of the substrate in turn, and a front gate is formed by adopting the etching technology; a back gate layer is grown on the lower surface of the substrate, and a back gate is formed by adopting the etching technology; and a lead-wire window is photoetched, metal is deposited and a lead-wire is photoetched so that a metal lead-wire of the source region, the drain region, the front gate and the back gate is formed, and finally the PNIN / NPIP type tensile strained germanium on insulator TFET with the abrupt tunneling junctions is formed.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a tension-strained germanium TFET on a PNIN / NPIP type insulating layer with an abrupt tunnel junction and a preparation method. Background technique [0002] The development of Integrated Circuit (IC) technology follows the "Moore's Law" and has entered the nanometer scale. Challenges from short channel effects, parasitic effects, and quantum tunneling make it increasingly difficult for traditional microelectronic device technology to meet The requirements for the continuous development of IC technology, especially the increasingly serious power consumption problem, have become the biggest bottleneck in the continuation of "Moore's Law". [0003] The tunneling field effect transistor (Tunneling Field Effect Transistor, referred to as TFET) adopts the physical mechanism of band-band tunneling, so that its sub-threshold swing breaks through the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/335H01L29/772H01L21/265H01L29/08H01L21/762
CPCH01L21/265H01L21/7624H01L29/08H01L29/0843H01L29/66409H01L29/772
Inventor 李妤晨
Owner XIAN UNIV OF SCI & TECH
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