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SSOI Tunneling Field Effect Transistor with Abrupt Tunneling Junction and Preparation Method

A technology of tunneling field effect and tunneling junction, which is applied in the manufacture of semiconductor/solid-state devices, semiconductor devices, electrical components, etc. It can solve the problems of small driving current, degradation of theoretical value of subthreshold slope, etc., and achieve the reduction of forbidden band width , Suppress bipolar effect, improve the effect of driving current

Inactive Publication Date: 2017-11-21
XIAN UNIV OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to overcome the problems of low driving current of existing Si-based TFET devices and degradation of subthreshold slope relative to the theoretical value, the present invention proposes a SSOI tunneling field effect transistor with abrupt tunneling junction and its preparation method

Method used

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  • SSOI Tunneling Field Effect Transistor with Abrupt Tunneling Junction and Preparation Method
  • SSOI Tunneling Field Effect Transistor with Abrupt Tunneling Junction and Preparation Method
  • SSOI Tunneling Field Effect Transistor with Abrupt Tunneling Junction and Preparation Method

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Embodiment 1

[0047] See figure 1 , figure 1 It is a flowchart of a method for preparing an SSOI tunneling field effect transistor with an abrupt tunnel junction according to an embodiment of the present invention, and the method includes the following steps:

[0048] Step a, preparing a strained silicon on insulator (Strained Silicon on Insulator, referred to as SSOI) substrate, the SSOI substrate sequentially includes the bottom layer of Si, the buried oxide layer and the top layer of strained Si;

[0049] Step b, forming shallow trench isolation in the top strained Si;

[0050]Step c, photolithographically forming a drain region pattern at a specified position on the strained Si surface of the top layer, and implanting ions to form a drain region by using an ion implantation process with glue;

[0051] Step d, using a dry etching process to form a trench in the source region at a position different from the specified position on the strained Si surface of the top layer;

[0052] Step ...

Embodiment 2

[0080] See Figure 2a-Figure 2h It is a schematic diagram of a method for preparing an SSOI tunneling field-effect transistor with an abrupt tunneling junction according to an embodiment of the present invention; this embodiment takes the preparation of an SSOI tunneling field-effect transistor with an abrupt tunneling junction as an example to illustrate, and the specific steps are as follows:

[0081] (1) Prepare an SSOI substrate. Such as Figure 2a As shown, the SSOI substrate includes a top strained Si layer 101 , a buried oxide layer 102 such as a buried silicon dioxide layer, and a bottom layer Si 103 .

[0082] (11) Epitaxially grow a graded SiGe layer on the Si wafer, then epitaxially grow a layer of relaxed SiGe layer with a fixed composition, and finally epitaxially grow a strained Si layer;

[0083] (12), implant a certain dose of H ions into the epitaxial layer, bond it with another Si sheet covered with an oxide layer in an ultra-high vacuum environment, and ca...

Embodiment 3

[0112] See image 3 , image 3 It is a schematic flow chart of a method for preparing an SSOI tunneling field effect transistor with an abrupt tunneling junction according to an embodiment of the present invention, taking the preparation of an N-type SSOI tunneling field effect transistor with an abrupt tunneling junction with a channel length of 45 nm as an example. In detail, the specific steps are as follows:

[0113] 1. Preparation of SSOI substrate

[0114] 1.1 Epitaxial growth.

[0115] Using selective epitaxy technology, a graded SiGe layer is epitaxially grown on a Si wafer at a high temperature of 800°C to 900°C, and the gas phase precursor GeH is dynamically adjusted during the epitaxial growth process. 4 and SiH 2 Cl 2 The flow rate ratio of the gradient SiGe layer is controlled to increase the Ge composition of the graded SiGe layer from 0 to the Ge composition of the relaxed SiGe layer of the fixed composition, and then a layer of fixed composition is epitaxi...

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Abstract

The invention relates to a strained-silicon-on-insulator (SSOI) tunneling field effect transistor with an abrupt tunnel junction and a preparation method thereof. The preparation method comprises: preparing an SSOI substrate; forming a shallow trench isolation unit; carrying out photoetching to form a drain region graph; carrying out adhesive ion implantation to form a drain region; carrying out dry etching to form a source region trench; depositing a Si material in a source region trench and carrying out in-situ doping to form a source region; forming a gate dielectric layer and a front gate layer on the upper surface of the substrate, carrying out etching to form a front gate, forming a back gate layer on the lower surface of the substrate, and carrying out etching to form a back gate; carrying out lead window photoetching, metal deposition, and lead photoetching to form source / drain and front / back leads. According to the invention, the drive current of the tunneling field effect transistor can be effectively improved and the sub-threshold slope can be reduced.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to an SSOI tunneling field effect transistor with an abrupt tunneling junction and a preparation method thereof. Background technique [0002] The development of Integrated Circuit (IC) technology follows the "Moore's Law" and has entered the nanometer scale. Challenges from short channel effects, parasitic effects, and quantum tunneling make it increasingly difficult for traditional microelectronic device technology to meet The requirements for the continuous development of IC technology, especially the increasingly serious power consumption problem, have become the biggest bottleneck in the continuation of "Moore's Law". [0003] The tunneling field effect transistor (Tunneling Field Effect Transistor, referred to as TFET) adopts the physical mechanism of band-band tunneling, so that its subthreshold swing is not limited by the limit value KT / ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/265H01L21/762H01L21/28H01L29/78H01L29/06H01L29/08H01L29/423
CPCH01L21/26506H01L21/7624H01L29/0688H01L29/0847H01L29/401H01L29/4232H01L29/66484H01L29/7831
Inventor 李妤晨
Owner XIAN UNIV OF SCI & TECH
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