Preparation method of gate-all-around transistor

Abstract

The invention provides a preparation method for a gate-all-around transistor, and the method comprises the steps: 1), providing an SOI substrate, and forming a groove in an insulating layer of the SOIsubstrate; 2) forming a semiconductor nanowire structure which is suspended and stretches across the groove; 3) rounding and thinning the semiconductor nanowire structure; 4) forming an injection barrier layer on the surface of the channel region, wherein the injection barrier layer exposes the preparation regions of the source region and the drain region; 5) performing an ion implantation process to form the source region and the drain region; 6) forming a fully-surrounded gate dielectric layer and a gate electrode layer on the surface of the semiconductor nanowire, and performing patterningto form a gate structure; and 7) forming a source electrode and a drain electrode. The gate-all-around transistor is prepared by adopting a gate-last process, so that the selection range of gate materials can be effectively widened, different device performance requirements are met, isotropic wet etching is not needed when the semiconductor nanowire is prepared, and a concave cavity can be effectively prevented from being generated.

Description

technical field [0001] The invention belongs to the field of semiconductor integrated circuit design and manufacture, and in particular relates to a preparation method of a gate-around transistor. Background technique [0002] As microelectronic devices continue to shrink, it is expected that the existing FinFET technology will face a large technical bottleneck at the 5nm and 3nm nodes, and the device performance will no longer be greatly improved as the device size continues to decrease. This requires us to adopt new device technologies, such as the use of new device materials (such as strained silicon, silicon germanium, germanium, III-V semiconductors, etc.), and the use of new device structures (such as nanowire gate-all-around transistors, etc.). [0003] The nanowire gate-all-around transistor can confine the conductive channel to the center of the nanowire instead of the interface between the nanowire and the gate oxide layer, which greatly reduces the scattering of c...

AI Technical Summary

Problems solved by technology

[0015] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for preparing a gate-all-round transistor, which is used to solve the problem of low process stability in the preparation of a gate-all-around transistor in the prior art

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