A nanowire transistor based on resonant tunneling and its preparation method

Abstract

The invention discloses a nanowire transistor based on resonance tunneling. The nanowire transistor comprises an SOI substrate, a tunneling barrier structure, a source region, a drain region, nanowires, a grid electrode, a source electrode, a drain electrode, a grid electrode and an insulating dielectric layer. The tunneling barrier structure is located on the buried oxide layer of the SOI substrate. The source region, the drain region and the nanowire are formed by etching top silicon of the SOI substrate; the nanowire is positioned between the source region and the drain region; wherein thesource region, the drain region and the nanowire are not directly connected and are connected through a tunneling barrier structure, the insulating dielectric layer is formed on the surfaces of the source region, the drain region and the nanowire, the grid electrode is formed on the insulating dielectric layer above the nanowire, the source electrode is formed on the source region, the drain electrode is formed on the drain region, and the grid electrode is formed on the grid electrode. According to the nanowire transistor structure based on resonance tunneling and the preparation method of the nanowire transistor structure, the sub-threshold slope is reduced, and large conduction current and small source-drain contact resistance can be achieved.

Description

technical field [0001] The invention relates to the technical field of manufacturing semiconductor devices, in particular to a nanowire transistor based on resonant tunneling and a preparation method thereof. Background technique [0002] With the continuous advancement of integrated circuit manufacturing technology, the size of metal oxide semiconductor field effect transistor (MOSFET) devices continues to shrink, and the current MOSFET technology node has entered 7nm. If the size of the device is to be further reduced, it is necessary to overcome many challenges in the principle and process of the device, such as the short channel effect and the fabrication of the PN junction. [0003] The preparation process of the junction-free silicon nanowire transistor is simple, and its source, drain, and channel regions are uniformly doped, and no junction is required to relieve the pressure caused by ion implantation and annealing in the ultra-steep junction. At the same time, the...

AI Technical Summary

Problems solved by technology

However, for conventional junction-free silicon nanowire transistors, its transport nature is still consistent with that of traditional MOSFETs, and its subthreshold slope is greater than 60mV / decade, and the off-state current of junction-free transistors is larger than that of traditional MOSFETs, increasing the Static power

[0004] Because tunneling transistors rely on quantum tunneling for transport, they can achieve very small off-state currents and sub-threshold slopes less than 60mV / decade. However, tunneling transistors are mostly realized by structural design, and the structure is complex, which is difficult to meet the requirements of smaller technology nodes. Require

Therefore, if the advantages of the two can be combined, a device with better performance can be prepared with a simpler process, which is of great research value, but nanowire transistors based on tunneling have not yet been reported.

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