The invention discloses an anti-staggered-layer 
heterojunction resonance tunneling field-effect 
transistor (TFET) and a preparation method thereof. The TFET comprises a tunneling source region, a channel region, a drain region and a 
control grid located above the channel region, wherein an 
electronic band structure of a heterogeneous tunneling junction of the tunneling source region and an 
electronic band structure of a heterogeneous tunneling junction of the channel region are respectively an anti-staggered-layer 
heterojunction. If the TFET is an N type device, the bottom of a 
conduction band of the tunneling source region is located below the 
valence band top of the channel region at the juncture surface of the heterogeneous tunneling junction of the tunneling source region and the heterogeneous tunneling junction of the channel region; if the TFET is a P type device, the 
valence band top of the tunneling source region is located above the bottom of a 
conduction band of the channel region. Thus, on-state currents of the TFET can be remarkably increased; meanwhile, off-state currents of the device are effectively suppressed, and a steep 
subthreshold slope is maintained. According to the preparation method of the TFET, a low-power dissipation 
integrated circuit formed by TFETs is prepared by effectively using a standard process, production cost is greatly reduced, and the process is simple.