53 results about "Contact barrier" patented technology

The invention relates to a cadmium telluride solar cell and a preparation method thereof, the cadmium telluride solar cell comprises a TCO layer, a buffer layer, a window layer, a light absorption layer, a back electrode layer and a back contact layer, the back contact layer is located between the light absorption layer and the back electrode layer, and the back contact layer is made of boron or carbon doped transition metal nitride. The back contact layer made of boron or carbon doped transition metal nitride is introduced between the light absorption layer and the back electrode layer, and transition gold elements in the back contact layer can be compatible with the cadmium telluride absorption layer, so that the obstruction of a contact barrier to hole transport is reduced, the interface characteristic between the CdTe absorption layer and the back contact layer is optimized, and the light emitting efficiency is improved. According to the present invention, the cadmium telluride absorption layer can form the good ohmic contact with the cadmium telluride absorption layer, such that the effect of the back field buffer layer can be provided so as to reflect the photo-induced electrons on the back surface in the cadmium telluride to the PN junction, such that the recombination of the electrons on the back surface can be substantially reduced, and the carrier collection efficiency of the cell can be improved so as to improve the open-circuit voltage and the conversion efficiency of the cell;

A trench cell structure having Schottky barriers and a preparation method thereof are provided. The trench cell structure includes a silicon substrate. A back metal layer is disposed on a back surface of the silicon substrate. The silicon substrate is heavily doped. A body region, a dielectric layer, and a front metal layer are sequentially disposed on a front surface of the silicon substrate from bottom to top. The drift region is lightly doped. Deep trench regions and a shallow trench region are defined on the body region at intervals. The deep trench regions and the shallow trench region include shielding electrodes and ohmic contact structures. The Schottky contact barriers are disposed between the deep trench regions and the shallow trench region, which reduces anode carrier injection efficiency when the trench cell structure is forwardly conducted, reduces reverse recovery charge, and reduces a reverse recovery time.

A semiconductor device includes a substrate; a channel layer over the substrate; a gate stack and a gate spacer pattern over the channel layer; an interlayer insulating layer covering the gate stack and the gate spacer pattern; and a contact pattern vertically passing through the interlayer insulating layer to be connected to the substrate. the contact pattern includes a contact plug; and a contact barrier layer surrounding a side surface of the contact plug. The contact barrier layer includes a protrusion portion protruding toward the channel layer in a horizontal direction.

The invention discloses a self-rectification ferroelectric memristor based on ferroelectric surface external polarization and a preparation method thereof. The memristor is of a vertical structure comprising an upper electrode layer, a ferroelectric layer and a semiconductor layer from top to bottom, the ferroelectric layer is a ferroelectric semiconductor with out-of-plane ferroelectric polarization; the out-of-plane polarization direction of the ferroelectric layer is perpendicular to the upper electrode layer / ferroelectric layer interface and the ferroelectric layer / semiconductor layer interface at the same time, the two contact surfaces form an asymmetric barrier, and the out-of-plane polarization state of the ferroelectric layer can be changed through external voltage, so that the barrier height of the two contact surfaces is changed, meanwhile, the carrier transport characteristic of the semiconductor layer is changed, and the performance of the device is improved. And therefore, a function of regulating and controlling the conductivity state of the memristor is achieved. The conduction current of the memristor is measured through a peripheral circuit and is used as a storage value. High-resistance and low-resistance switching and rectification characteristics are realized by utilizing the change of the contact potential barrier of the ferroelectric layer and the silicon interface in the polarization overturning process. The memristor is simple in structure, easy to integrate and low in power consumption.

The invention discloses a PEDOT: PSS / n-Si solar cell with a MoOx multifunctional interface layer and a preparation method of the PEDOT: PSS / n-Si solar cell. Comprising the following steps: (1) preparing a photovoltaic device by adopting a monocrystalline silicon wafer; (2) adding DMSO and a surfactant Triton X-100 into the PEDOT: PSS aqueous solution, and carrying out magnetic stirring to prepare a precursor solution; (3) removing surface oxides from the n-type silicon wafer by using an HF solution; then, deionized water is used for cleaning the HF acid solution left on the silicon wafer, and finally nitrogen is used for purging and drying the silicon wafer; (4) spin-coating the PEDOT: PSS precursor solution prepared in the step (2) on the surface of the silicon wafer, and then annealing to form a film; (5) depositing a layer of MoOx film on the PEDOT: PSS film obtained in the step (4) by adopting a thermal evaporation method; (6) preparing an Ag grid line electrode on the PEDOT: PSS / MoOx thin film; and (7) depositing a layer of metal electrode on the back surface of the sample obtained in the step (6). According to the invention, Ag is in contact with MoOx to form an Ag / MoOx electrode, so that the contact potential barrier between PEDOT: PSS / Ag is reduced. The solar cell manufacturing method is simple and easy to implement, and can be used for large-scale production.

The invention relates to the technical field of solar cells, in particular to a solar cell, a preparation method thereof and a photovoltaic module. The solar cell of the present application comprises: a silicon substrate; the silicon substrate is provided with a first surface and a second surface which are oppositely arranged; the first intrinsic layer, the N-type doped layer and the first transparent conductive film layer are sequentially arranged on the first surface of the silicon substrate; the second intrinsic layer, the P-type doped layer and the second transparent conductive film layer are sequentially arranged on the second surface of the silicon substrate; and the P-type doped layer comprises a first P-type doped layer, a second P-type doped layer and a third P-type doped layer which are arranged in sequence. According to the solar cell, carrier transportation can be enhanced, a hole contact barrier is reduced, and the conversion efficiency of the cell is remarkably improved.

A semiconductor device includes an inter-layer dielectric layer over a substrate; a first contact plug structure coupled to a first active region of the substrate by vertically penetrating the inter-layer dielectric layer, and a second contact plug structure coupled to a second active region of the substrate. The first contact plug structure includes a first metal silicide layer; a first contact barrier layer over the first metal silicide layer; and a first contact plug over the first contact barrier layer. The second contact plug structure includes a second metal silicide layer; a second contact barrier layer over the second metal silicide layer; and a second contact plug over the second contact barrier layer. The first and second metal silicide layers include different metal silicides. The first metal silicide layer has a wider horizontal width and a greater vertical height than the second metal silicide layer.

The present invention discloses a back-contact heterojunction solar cell and a manufacturing method thereof, and relates to the technical field of solar cells, so as to simultaneously reduce the contact barrier between the P-type region and the first electrode, and the contact barrier between the N-type region and the second electrode in the back-contact heterojunction solar cell to a smaller target range, thereby improving its photoelectric conversion efficiency. The back-contact heterojunction solar cell comprises: a silicon heterojunction substrate, a first transparent conductive layer, and a second transparent conductive layer. The silicon heterojunction substrate has a first surface and a second surface opposite to each other. Along a direction parallel to the second surface, the second surface has a P-type region and an N-type region alternately arranged at intervals. The first transparent conductive layer is at least formed on the P-type region. The second transparent conductive layer is at least formed on the N-type region. The portion of the second transparent conductive layer located on the N-type region is insulated from the portion of the first transparent conductive layer located on the P-type region. The work function of the second transparent conductive layer is less than the work function of the first transparent conductive layer.

The invention discloses an SBD integrated silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) capable of improving reverse freewheeling capability and a preparation method thereof. The device sequentially comprises a silicon carbide substrate, an N-type drift layer and an N-type carrier storage layer from bottom to top, the N + regions and the P + regions are alternately distributed at the upper part of the N-type carrier storage layer; the deep groove penetrates through the N + region and the P + region, and the bottom of the deep groove is located in the N-type carrier storage layer; the P-type buried layer is formed in the N-type carrier storage layer at the bottom of the deep trench; the source electrode is used for filling the deep grooves on the two sides of the central N + region and realizing a Schottky contact barrier with the N-type carrier storage layer on the side wall; the gate oxide layer covers the side wall and the bottom of the deep trench on the outermost side; the grid electrode covers the gate oxide layer and fills the deep groove on the outermost side; the P-type base region is formed in the N + region between the grid electrode and the source electrode and in the N-type carrier storage layer below the P + region; the passivation layer covers the surface of the grid electrode; and a source ohmic contact covering the surface of the device.

The electrical connector and assembly may include a housing and contact members therein. The contact members include electrical contacts. A contact barrier is connected to the housing and movable between a closed state and an open state. In the open state, the contact members are exposed, and in the closed state, the contact members are protected by the contact barrier. The contact barrier is biased to the closed state. The electrical connector and assembly may include a housing with a core assembly having at least one electrical contact. The rotatable coupling member is rotatably mounted to an end of the housing and includes the coupling housing, at least one latch element coupled to an inner surface of the coupling housing, and at least one central biasing element configured to bias and self-center the rotatable coupling member relative to the housing in a connection-ready orientation.

The present application discloses a semiconductor device with adjustment layers and a method for fabricating the semiconductor device with the adjustment layers. The semiconductor device includes a substrate, an interconnection structure positioned on the substrate, a contact positioned penetrating the interconnection structure, two adjustment layers positioned on sidewalls of the contact, a contact barrier layer positioned between the interconnection structure and the contact and between the substrate and the contact, wherein the two adjustment layers are positioned between the contact and the contact barrier layer. A bottom segment of the contact barrier layer is positioned between the substrate and the contact, and bottom most points of the two adjustment layers contact the bottom portion of the contact barrier layer.

A MQW LED active layer configured to emit deep UV light is contacted on its p-side by a Mg doped p-AlGaN electron blocking layer, a Mg doped p-AlN hole injection layer of 1-10nm thickness, a Mg doped p-GaN contact layer of 1-20nm thickness, and a p-side electrode contact. The contact layer can also be a one-dimensional nanowire or nanotube layer, a graphene layer, a two-dimensional selenide layer, a conductive oxide, amorphous carbon, or an aluminium free nitride semiconductor layer which is a contact barrier regulator.

A method of fabricating a semiconductor device includes: forming an active pattern on a substrate, forming a source / drain pattern on the active pattern, forming a contact hole on the source / drain pattern, forming a contact barrier layer, which has an upper surface of a first height based on a bottom surface of the contact hole, in the contact hole, forming a passivation layer on the contact barrier layer in the contact hole, forming a mask layer on the passivation layer in the contact hole, removing an upper portion of the contact barrier layer so that an upper surface of the contact barrier layer has a second height lower than the first height, removing the passivation layer and the mask layer, and forming a contact filling layer, which covers the upper surface of the contact barrier layer and fills the contact hole, in the contact hole.

The present invention relates to the field of semiconductor detection technology, and provides a four-probe measuring instrument, a four-probe measuring system, and a method for measuring a silicon wafer to be tested by a four-probe measuring instrument, wherein the four-probe measuring instrument comprises: four probes; a conductive plate, the conductive plate having holes opposite to the probes, the probes passing through the holes; a voltage controller connected to the conductive plate, used to output a stable voltage to the conductive plate; a host computer, used to send instructions to the voltage controller to control the operation of the voltage controller. The present invention makes the conductive plate carry an electric potential, and under the action of the electric field, the carrier concentration on the surface of the semiconductor increases, thereby reducing the contact barrier on the semiconductor surface, improving the contact characteristics, and making the probe form a good ohmic contact with the surface of the silicon wafer to be tested, thereby improving the stability of silicon wafer measurement.

To provide a semiconductor device that can prevent a contact barrier metal film from peeling off from a trench gate extraction electrode.SOLUTION: In a gate wiring lead-out region MGR defined in a semiconductor substrate SUB, a protrusion PRT protruding toward a gate lead-out contact member GCN is formed in a trench gate lead-out electrode TGI. The protrusion PRT is formed of a native oxide film SSM and a polysilicon film PSF. The gate lead-out contact member GCN is formed to cover the protrusion PRT with a barrier metal film BME interposed therebetween at the protrusion PRT.SELECTED DRAWING: Figure 4

The application provides a power module Schottky diode chip structure and a preparation method thereof, and the chip structure comprises an As-doped silicon semiconductor substrate and a P-doped silicon semiconductor epitaxial layer located above the silicon semiconductor substrate; the edge of the chip structure is an oxide layer passivation layer structure, and the main junction of the chip is a composite junction barrier structure formed by a ring-shaped P+, a hexagonal P+ and a platinum-silicon Schottky junction; a front multi-layer metal electrode is arranged on the front surface of the composite junction barrier structure, and a multi-layer metal electrode is arranged on the back surface of the silicon semiconductor substrate; the method is simple, low in cost, practical and effective, the NiPt alloy is used as a Schottky barrier metal to form a composite metal silicide-silicon contact barrier (NiPtSi-Si), the barrier height is low, the reverse current is small, and the barrier height can be adjusted by adjusting the alloy component.

A semiconductor device includes a substrate including an active region extending in a first direction, a gate structure extending in a second direction intersecting the active region on the substrate, a source / drain region in a recessed region of the active region on at least one side of the gate structure, a first conductive structure connected to the source / drain region, and a first contact spacer. The first conductive structure includes a first interconnection portion, a first via portion extending from a lower surface of the first interconnection portion, and a first contact barrier layer on a lower surface of the first interconnection portion and a side surface and a lower surface of the first via portion. The first contact spacer extends along at least a portion of a side surface of the first via portion below the first interconnection portion.

A semiconductor structure includes a semiconductor substrate, a dielectric layer, a tungsten plug, a conductive plug, and a contact barrier. The dielectric layer is over a semiconductor substrate. The tungsten plug is in the dielectric layer. The conductive plug is on the tungsten plug. The contact barrier includes a sidewall barrier on a sidewall of the conductive plug and a bottom barrier between the conductive plug and the tungsten plug. A thickness of the sidewall barrier is greater than a thickness of the bottom barrier.

To provide a semiconductor device capable of preventing a contact barrier metal film from peeling off from the trench gate lead-out electrode. In the gate wiring lead-out region MGR defined on a semiconductor substrate, a convex portion is formed on the trench gate lead-out electrode TGI, extending towards a gate lead-out contact member. The convex portion is formed by a natural oxidation film and a polysilicon film PSF. The gate lead-out contact member is formed to cover the convex portion by interposing the contact barrier metal film.

Electrical connectors and assemblies may include a housing and contact members therein. The contact member includes an electrical contact. A contact barrier is connected to the housing and is movable between a closed state and an open state. In the open state, the contact member is exposed, and in the closed state, the contact member is protected by the contact barrier. The contact barrier is biased into the closed state. An electrical connector and assembly may include a housing having a core assembly having at least one electrical contact. A rotatable coupling member is rotatably attached to an end of the housing and includes a coupling housing, at least one latch element coupled to an inner surface of the coupling housing, and at least one central biasing element, the at least one central biasing element is configured to bias and self-center the rotatable coupling member relative to the housing to an orientation ready for connection.

According to the TBC battery and the preparation method thereof, boron-doped carrier selective contact areas and phosphorus-doped carrier selective contact areas are sequentially constructed on the back surface of a silicon wafer, and the synergistic effect of a tunneling oxide layer and a polycrystalline / amorphous silicon film is combined, so that efficient blocking of minority carriers and selective transmission of majority carriers are effectively realized; and the interface recombination loss is obviously inhibited, so that the open-circuit voltage and the filling factor of the battery are greatly improved. On the basis, strontium titanate is introduced as a passivation layer material, and after the strontium titanate is matched with an alkyl modification layer formed on the surface of the strontium titanate, the chemical stability and environmental durability of the passivation layer are improved, the interface energy band structure between the passivation layer and a subsequent metal electrode is optimized, the contact barrier and the contact resistance are remarkably reduced, and the service life of the solar cell is prolonged. And efficient extraction and transverse transportation of majority carriers are promoted. Therefore, excellent surface passivation performance can be achieved, and meanwhile good interface compatibility, low contact resistance and long-term operation stability are achieved.

The application relates to the technical field of thin-film batteries, and discloses a cadmium telluride thin-film battery and a preparation method thereof. The cadmium telluride thin-film battery comprises, from bottom to top, a base layer, a conductive layer, a high-resistance layer, a window layer, an absorption layer, a first back contact layer, a second back contact layer and a back electrode layer. The first back contact layer comprises a first back contact layer material doped with a first element, and the second back contact layer comprises a second back contact layer material doped with a second element. The doping content of the second element is higher than that of the first element. The first element has a low content and diffuses to the absorption layer, reduces Cu defects introduced by excessive doping, improves the performance of the absorption layer and the stability of the battery. The second element has a high content, which is beneficial to increasing the carrier concentration and conductivity of the second back contact layer, improving the contact performance between the second contact layer and the first back contact layer and the back electrode layer, reducing the contact barrier, improving the hole carrier transport, and improving the efficiency and stability of the battery.

A semiconductor device includes a back interlayer insulating film, a back wiring line disposed within the back interlayer insulating film, a fin-type pattern disposed on a first surface of the back wiring line, a source / drain pattern disposed on the fin-type pattern, and a back wiring contact connecting the back wiring line and source / drain pattern. A bottom surface of the source / drain pattern is connected to the fin-type pattern and faces the back wiring line. The back wiring contact includes a back contact barrier film, a back contact plug film, and a back ferroelectric material film. The back wiring contact includes a third surface facing the back wiring line. A vertical length from a second surface of the back wiring line to the third surface of the back wiring contact is less than a vertical length from the second surface to the bottom surface of the source / drain pattern.

The invention provides a PtAu-TiAu-PtAu multilayer film electrode and a preparation method thereof. The method comprises the following steps: S1, growing a PtAu bottom layer in an electrode photoetching pattern area of a wafer; s2, growing a TiAu seed layer on the whole surface of the wafer in the S1; s3, growing a PtAu surface layer in the electrode photoetching pattern area of the wafer in the S2; and S4, electroplating a thick Au layer on the PtAu surface layer. According to the invention, the Pt and Au high-work-function material is used as the PtAu bottom layer which can form better ohmic contact with the chip contact layer, so that the chip contact barrier is reduced, and the ohmic contact resistance of the electrode and the overall resistivity of the body material are reduced; multiple layers of electrodes grow step by step, the abnormity of residual Au at the edge of a pattern caused by one-time stripping can be further reduced, Au is used as a protective layer and a transition layer of other metals in each growing layer, the oxidation pollution of the electrodes is effectively prevented, and the film layer stress, the abnormal risk of electrode stripping and the resistance value of a bulk resistor can be reduced through electrode alternation; and the TiAu seed layer is deviated from the bottom layer, so that process reworking is facilitated, and the reworking rejection rate is reduced.

The utility model discloses an IGBT (Insulated Gate Bipolar Transistor) mounting device, a suction nozzle main shaft is rotatably mounted and connected with a first fixed shaft and is provided with a plurality of rotary mounting positions, the front end of the first fixed shaft is mounted and connected with a second fixed shaft vertical to the suction nozzle main shaft, and the first fixed shaft is vertically mounted and connected with a third fixed shaft through a connector; the third fixing shaft is parallel to the suction nozzle main shaft, and the lower end of the third fixing shaft is connected with a baffle which is perpendicular to the lead frame slide holder. The side face of the baffle is located outside the side edge of the chip in the horizontal direction and is spaced from the side edge of the chip so as to accommodate overflowing welding flux. The lowest end of the third fixing shaft abuts against and makes contact with the lead frame slide holder, a contact blocking area is formed to block welding flux from overflowing outwards, and the third fixing shaft is provided with a plurality of horizontal and vertical axial installation positions. Meanwhile, a plurality of mounting and adjusting positions are arranged in a plurality of linear directions and circumferential directions, so that the device is suitable for different production application scenes, simple in structure, high in applicability and reliable in production quality.

The invention relates to a semiconductor device and a manufacturing method thereof. To provide a semiconductor device capable of preventing a contact barrier metal film from being peeled off from a trench gate extraction electrode. In a gate wiring lead-out region MGR defined on a semiconductor substrate, a convex portion is formed on a trench gate lead-out electrode TGI and extends toward a gate lead-out contact member. The convex portion is formed by a natural oxide film and a polysilicon film PSF. The gate lead-out contact member is formed to cover the convex portion by inserting the contact barrier metal film.

A semiconductor structure includes a semiconductor substrate, a dielectric layer, a tungsten plug, a conductive plug, and a contact barrier. The dielectric layer is over a semiconductor substrate. The tungsten plug is in the dielectric layer. The conductive plug is on the tungsten plug. The contact barrier includes a sidewall barrier on a sidewall of the conductive plug and a bottom barrier between the conductive plug and the tungsten plug. A thickness of the sidewall barrier is greater than a thickness of the bottom barrier.

To provide a semiconductor device capable of preventing the detachment of a contact barrier metal film from the trench-gate lead electrode, a convex section is formed on the trench-gate lead electrode (TGI) within the gate wiring lead region (MGR) defined on a semiconductor substrate. This convex section extends towards a gate lead contact element. The convex section consists of a natural oxide film and a polysilicon film (PSF). The gate lead contact element is designed to cover the convex section by arranging the contact barrier metal film.

The application provides a chip and a preparation method of the chip. The chip comprises a substrate and a transistor. The transistor comprises a channel structure, a first electrode, a second electrode, a first doped layer and a gate. At least part of the first electrode is located on one side of the channel structure, and the first electrode is a source electrode or a drain electrode. At least part of the second electrode is located on one side of the channel structure, and the second electrode is a source electrode or a drain electrode. At least part of the first doped layer is located on one side of the channel structure, away from the first electrode and the second electrode. The gate is located on at least one side of the channel structure. By arranging at least part of the first doped layer and at least part of the electrode (the first electrode and the second electrode) on two sides of the channel structure respectively, the doped layer can more effectively dope the channel structure, the contact barrier of the channel structure is thinned, the contact resistance between the electrode and the channel structure is reduced without introducing additional parasitic effects, and the performance of the chip is improved.