41results about How to "Decrease the density of surface states" patented technology

The invention relates to the field of microelectronic technology, a method for improving the ohmic contact characteristics of a silicon carbide semiconductor, comprising the following steps: (1) performing traditional RCA cleaning on a silicon carbide sample; (2) placing the silicon carbide sample in electron cyclotron resonance microwave plasma In the bulk system, hydrogen plasma treatment is carried out; (3) electrode pattern is formed on the silicon carbide sample by photolithography; (4) metal electrode material titanium or titanium carbide is deposited by magnetron sputtering; (5) The silicon sample was stripped of metal other than the electrodes in an ultrasonic cleaner with acetone, and dried with nitrogen; (6) the silicon carbide sample was annealed in a nitrogen atmosphere. In the present invention, after pre-treating the surface of silicon carbide with hydrogen plasma generated by an electron cyclotron resonance system, the surface of silicon carbide is effectively cleaned and passivated, and the surface state density is significantly reduced, and combined with low work function metal titanium or titanium carbide and relatively The silicon carbide substrate with high doping concentration has a low barrier height of Ti/SiC contact, and good ohmic contact can be formed under low temperature annealing conditions.

The invention discloses a crystalline silicon battery surface passive film and a manufacturing method of the crystalline silicon battery surface passive film. The crystalline silicon battery surface passive film comprises a first silicon oxide film, a silicon nitride film and a second silicon oxide film. The silicon nitride film is deposited on the first silicon oxide film. The second silicon oxide film is deposited on the silicon oxide film. The thickness d1 of the first silicon oxide film is 10 nm-30 nm. The thickness d2 of the silicon nitride film is 30 nm-50 nm. The thickness d3 of the second silicon oxide film is 25 nm-50 nm. The probability of light full reflection is substantially increased, and namely more light enters a silicon wafer, so that more charge carriers are generated, and battery efficiency is improved.

The invention relates to a preparation method of a concentrating solar cell chip capable of preventing edge leakage and the method adopts the accurate half-cutter cutting method. The method comprises the following steps: the half-cutter cutting blade of which cutting edge has an inclined side is used to cut a groove along the cutting street of the battery chip, wherein the side wall of the groove also has a certain angle of inclination; chemical polishing is performed to the side wall of the groove; a transparent insulation material used as the anti-reflection film is covered on the surface of the battery chip, the surface of battery chip is passivated to avoid current leakage; and a conventional blade of which edge width is less than that of the half-cutter cutting blade is used to scratch the chip and form a single solar battery chip. The cutting blade of which edge has an angle of inclination is used to perform half-cutter cutting to the chip so that the side wall of the cutting street has the same angle of inclination, the chip can be prevented from damaging during the scratching process and a passivating film with high quality and reflecting property can be prepared on the chip; the width of the blade used for scratching the chip is less than that of the half-cutter cutting blade, thus preventing that the passivating film is damaged during the scratching process; and good passivation edge of the solar battery chip can be obtained and the edge leakage can be prevented.

A multilayer compound semiconductor is contacted with an electrically conducting fluid, and a current is passed between the semiconductor and the fluid. The current passes is monitored, and the current is controlled in response to the monitoring.

The invention discloses a planar indium gallium arsenic light-sensitive chip with surface passivation improved and a manufacturing method. According to the structure of the planar indium gallium arsenic light-sensitive chip, an N-type InP layer, an indium gallium arsenic intrinsic absorption layer, an N-type InP cap layer, a SiNx passivation layer, a P-electrode and a thickened electrode (8) are grown on a semi-insulating InP substrate in sequence. The manufacturing process is improved on the basis of an original process, and comprises removal and vulcanization of a diffusion mask and silicon nitride passive film growing through an inductive coupling plasma chemical vapor deposition (ICPCVD) technology. The planar indium gallium arsenic light-sensitive chip with surface passivation improved and the manufacturing method have the advantages the passivation layer of the chip is even in structure; the surface state density of a device is effectively reduced, and the surface can be prevented from being oxidized again through a vulcanization film formed on the surface; damage of the process to the surface of materials is small, the film is compact and is in stress fit with the substrate, the element bonding state is good, and the passivaition effect is excellent.

The invention discloses a semiconductor laser material passivation method. The method is applicable to passivation treatment of a cavity surface material of a semiconductor laser resonant cavity; themethod specifically comprises the steps of performing bombardment cleaning on the cavity surface material of the semiconductor laser resonant cavity by adopting ion beams, and depositing an AlN passivation layer on the cavity surface of the semiconductor laser resonant cavity by adopting an ALD technology. According to the semiconductor laser material passivation method disclosed in the invention,the surface of the resonant cavity is bombarded by the ion beams in a vacuum environment to effectively remove an oxide layer form the cavity surface, cavity surface pollutants, surface state, surface material dislocation and surface material dangling bond to obtain a clean semiconductor laser resonant cavity surface, and then low-temperature deposition in an ALD apparatus is realized in a plasmaauxiliary condition to obtain the AlN passivation layer for protecting the cavity surface of the resonant cavity. By virtue of the method disclosed in the invention, by performing process treatment on the resonant cavity surface, the cavity surface damage threshold value of the semiconductor laser is improved, and improvement of the output power, the service life and performance stability of thedevice is realized.

The invention discloses a method improving a manufacturing process of a crystalline silicon solar cell through arsenic ion implantation. On one hand, an N-type area is formed on the surface of the crystalline silicon solar cell through arsenic ion implantation, the crystalline silicon solar cell has high doping and shallow junction functions simultaneously, the open-circuit voltage and cell efficiency are improved, high-dose arsenic does not cause too many defects to the surface of silicon after annealing in contrast with phosphorus, reduction of the surface state density of a silicon chip is facilitated, and the service lives of minority carriers are prolonged; and on the other hand, metal of the silicon chip is in ohmic contact with the silicon chip in a traditional diffusion junction mode, the method is completely compatible with the conventional diffusion junction and screen printing sintering technology in the field of manufacture of photovoltaic cell, new parameters do not need exploring, and mass production can be achieved.

The invention discloses a surface modification method for an SnO<2>-based photo-anode, and belongs to the field of photoelectrochemistry. The surface modification method comprises the following implementation steps: (1) dissolving soluble chromic acid or chromate containing high-valent chromium into water to prepare a chromic acid or chromate solution a containing the high-valent chromium; (2) preparing a water solution b of a non-oxidizing acid with certain concentration; (3) soaking an SnO<2> mesoporous thin film of which the surface is subjected to hydrophilizing treatment into the solution a for a certain period of time, taking out and soaking the SnO<2> mesoporous thin film into deionized water or washing the SnO<2> mesoporous thin film with the deionized water, soaking the SnO<2> mesoporous thin film into the solution b for a certain period of time, taking out and soaking the SnO<2> mesoporous thin film into the deionized water or washing the SnO<2> mesoporous thin film with the deionized water, and drying the SnO<2> mesoporous thin film at a certain temperature; and (4) repeating the step (3) for a plurality of times, drying and burning the SnO<2> mesoporous thin film to obtain the SnO<2>-based photo-anode subjected to CrO<x> surface modification. The effect improvement of the SnO<2>-based photo-anode prepared by the method disclosed by the invention is obvious; and the method is simple to operate and easy to implement.

The invention provides a transistor groove manufacturing method and a transistor. The method comprises the following steps: epitaxially growing an epitaxial layer above a substrate; transferring the two-dimensional material layer above the epitaxial layer, continuing to epitaxially grow the epitaxial layer, and forming a first groove by the two-dimensional material layer and the epitaxial layer; epitaxially growing a first barrier layer and a second barrier layer above the epitaxial layer and on two sides of the first groove; and depositing a dielectric layer above the two-dimensional materiallayer, the first barrier layer and the second barrier layer to form a second groove. According to the groove system of the transistor manufactured through the method, the surface of the groove is smoother, and the surface state density is lower.

The invention discloses a method for preparing a III-nitride Schottky barrier diode (SBD) which is provided with a thick film and is low in defect density and high in pressure resistance. A method of selection region epitaxial growth is utilized for the III-nitride SBD. The III-nitride SBD structurally sequentially comprises a bottom layer substrate, a dielectric layer, a III-nitride three-dimensional structure, a side wall barrier layer, a Schottky contact layer and an Ohmic contact layer from bottom to top, wherein the dielectric layer is provided with a selection region growth window; the III-nitride three-dimensional structure is obtained by utilizing the selective epitaxial growth; and the side wall barrier layer is used for preventing electric leakage. The three-dimensional III-nitride structure obtained through the selective epitaxial growth method is large in thickness and lower in defect density, the SBD has a lower reverse leakage current and higher reverse breakdown voltage; the III-nitride SBD is simple in structure, the parallel connection packaging of multiple devices is achieved easily, and the method has wide prospect in the aspect of high-current high-voltage resistant SBD devices.