43 results about "Junction formation" patented technology

The invention provides a method for detecting silicon single crystal COP free area distribution, and relates to the technical field of silicon single crystal quality detection.The method comprises the steps that a silicon wafer to be detected is cleaned to obtain a first silicon wafer; uniformly smearing a transition metal ion solution on the surface of the first silicon wafer to obtain a second silicon wafer; placing the second silicon wafer in a high-temperature environment, and performing heat treatment under three temperature gradients to obtain a third silicon wafer; wherein in the first stage, transition metal ions are diffused to the surface layer of the silicon wafer to activate oxygen precipitates in a Pv region, in the second stage, the transition metal ions are promoted to be diffused into the silicon wafer to develop a Pi low-oxygen region, and in the third stage, nuclei coalescence in a B-band region is activated at high temperature to form a differential arrangement ring; cleaning the third silicon wafer through a mixed acid solution to obtain a fourth silicon wafer; and placing the fourth silicon wafer in a preferential corrosion liquid for preferential corrosion, and carrying out COP free area distribution detection on the obtained detection sample wafer. According to the scheme, the definition of each region boundary can be improved, so that the detection accuracy of COP free region distribution is improved.

An optical modulator includes a substrate defining a plane and first, second, and third PN junctions formed on the substrate. The first PN junction is formed on the substrate by a first region doped with a p-type doping abutting a second region doped with an n-type doping. The second PN junction is formed on the substrate adjacent to the second region of the first PN junction. The third PN junction is formed on the substrate adjacent to the first region of the first PN junction.

The invention discloses a composite MOSFET photoelectric detector based on a mixed dimensional material, and belongs to the field of photoelectric detection. A built-in electric field in a PN junction at the top end of the detector enables a photon-generated carrier to be collected by graphene, so that a junction region carrier of a PN junction at the bottom end is influenced by high-k hexagonal boron nitride, and a light-driven MOSFET structure is formed; the PbSe quantum dots expand the detection wavelength range of the device. A built-in electric field formed by the PN junction at the bottom end enables photon-generated carriers to be separated and generate intrinsic response; the one-dimensional material can detect polarized light, has a small cross sectional area, and effectively inhibits dark current. Meanwhile, the two PN junctions can be controlled through the top grid electrode, so that the device works in an amplification region of the MOSFET, and the light response is linearly amplified. According to the invention, optical gating is effectively avoided, and a polarization, broadband, high-sensitivity and high-speed detector is realized.

The application discloses a method for realizing an integrated ultrahigh-temperature environmental barrier composite coating. After a high-entropy alloy or boride layer and a molybdenum metal pre-coating layer are pre-coated on the surface of a substrate, a silicon-boron co-embedding deposition is carried out through a pre-oxidation process to form an ordered Mo-Si-B multilayer structure in the molybdenum metal layer. A composite coating formed by a metal silicide and silicon dioxide is cold sprayed on the Mo-Si-B multilayer structure to form a three-dimensional network structure composite self-healing layer through high-temperature sintering. An alloy oxide is cold sprayed or magnetron sputtered outside the composite self-healing layer to form a water vapor resistant layer. Through the integrated coating preparation process, the advantages of different components are complementary, and the effective protection of various refractory alloys in a wide temperature range (room temperature-1700 DEG C) can be realized.

The present invention relates to a broad-area diode laser (BAL) comprising an integrated p-n tunnel junction. The present invention in particular relates to a high-performance broad-area diode laser in which, in order to improve the beam quality and to reduce the thermal resistance, a p-n tunnel junction, biased in the reverse direction, is integrated in the layer system of the diode laser.A laser diode according to the invention comprises an active layer (20) formed between an n-doped semiconductor material (10, 12, 14) and a p-doped semiconductor material (30, 32, 34), the active layer (20) forming, along a longitudinal axis, an active zone for generating electromagnetic radiation; wherein at least one n-doped intermediate layer (50, 54) is arranged between an overlying p-side metal contact (52) and the p-doped semiconductor material (30, 32, 34), and, in the at least one n-doped intermediate layer (50, 54) in the region above the active zone, a p-n tunnel junction (40) being formed which is directly adjacent to the p-doped semiconductor material (30, 32, 34).

The present disclosure is directed to a structure of an optical modulator and a method of forming the structure. The structure includes first, second, third, and fourth doped regions forming a C-shaped P-N junction in an optical waveguide. The method of forming the structure includes applying a first mask to form the first doped region by implanting dopants of a first type on a side surface of the optical waveguide. The method further includes applying a second mask to form the second, third, and fourth doped regions at different depths under a top surface of the optical waveguide by implanting dopants of the first type and a second type. The P-N junction formed by the method is self-aligned and immune to inline overlay and critical dimensions of the first and second masks, providing an improved profile of the P-N junction and a reliable and consistent product.

According to the silicon-based PIN photodiode, the manufacturing method and the electronic device provided by the invention, the FZ single crystal is adopted as the substrate, and the doped region is formed in an ion implantation and annealing mode, so that the junction depth and the concentration can be effectively controlled. And thinning the silicon wafer by adopting a Taiko back thinning process. The photosensitive area adopts a shallow junction and deep junction combined structure, the shallow junction can increase the blue light absorption rate, and the deep junction forms ohmic contact. The anti-reflection layer adopts a silicon dioxide and silicon nitride double-layer structure, so that the surface stress of silicon / silicon nitride can be effectively relieved, and the reliability is improved. The cut-off region N + and the back N + can reduce dark current, and back metallization can form a back cathode.

Methods and structures are presented for mitigating back-gating effects in radio frequency (RF) silicon-on-insulator (SOI) substrates, RF-SOI. According to an aspect, a first implant or junction is formed in a region of a trap-rich layer (TRL) of the RF-SOI beneath a first circuit / device to be protected. The first implant or junction is entirely contained within the TRL. A planar surface area of the first implant and / or junction entirely contains a projection of a planar surface area of the first circuit and / or device. The first implant or junction is biased via a through-BOX contact (TBC) that penetrates a BOX layer at a shallow trench isolation region formed in the RF-SOI. According to another aspect, a second implant or junction is formed in a region of the TRL beneath a second circuit / device. The first implant or junction and the second implant or junction are not connected and are separated by an undoped region of the TRL.

Approaches herein provide devices, systems, and methods of transistor patterning using a frontside implant plus epitaxial process to form a graded junction having a high surface doping concentration for a vertical contact transistor bitline. One method may include delivering ions into a front side of a substrate of a transistor to form a graded junction in the substrate, wherein the substrate is maintained at a temperature greater than 100° C. while the ions are delivered into the substrate, and thermally treating the graded junction. The method may further include forming, after the graded junction is thermally treated, an epitaxial layer over the graded junction, forming a plurality of gates in the epitaxial layer, and processing a backside of the substrate to remove the substrate to the graded junction following formation of the plurality of gates.

The application provides a vertical semiconductor structure with integrated sampling structure and a manufacturing method thereof. The vertical semiconductor structure with integrated sampling structure comprises a vertical semiconductor structure cell, a sampling cell, a control electrode, a first electrode, a second electrode and a sampling electrode. According to an embodiment of the application, firstly, the sampling electrode can sample the voltage difference between the first electrode and the second electrode in real time; a PN junction is formed between the first / two P-type diffusion regions and the second N-type base region of the sampling cell, and the PN junction forms a potential barrier for blocking the electron emission of the sampling electrode, so that the voltage signal of the sampling electrode is input to a protection circuit, and the protection circuit can safely and quickly detect whether the vertical semiconductor structure is in a desaturation state when judging that the vertical semiconductor structure cell is in an open state. Secondly, a sampling resistor is connected in series between the sampling electrode and the first electrode, and the positive voltage of the sampling electrode can increase the height of the potential barrier, so as to ensure the stable work of the sampling cell.

A semiconductor device includes a device region, including a source contact, a drain contact formed on a substrate, and a gate contact formed between the source contact and the drain contact; an isolation region surrounding the device region, the isolation region including an N-type semiconductor region formed on the substrate, a first silicide layer and a second silicide layer formed in the N-type semiconductor region and separated from each other by an isolation layer, and an anode contact and a cathode contact connected to the first silicide layer and the second silicide layer, respectively; and a Schottky barrier diode formed inside the isolation region by a junction of the first silicide layer and the N-type semiconductor region. The anode contact is connected to the source contact, and the cathode contact is connected to the drain contact.

One or more gated nanosheet diodes are disposed on a substrate and made from a nanosheet structure. A first (second) source / drain (S / D) is disposed on the substrate. The first (second) S / D has a first (second) S / D doping concentration of a first (second) S / D doping type. One or more p-n junctions form one or more respective diodes. Each of the p-n junctions has a first side and a second side. The first (second) side of the p-n junction is electrically and physically connected to the first (second) S / D and has a same type of doping, respectively. A gate stack made from a gate dielectric layer and a gate metal interfaces and surrounds each of the p-n junctions.

Provided in the present application are a solar cell, a manufacturing method therefor and a photovoltaic module. The solar cell comprises: an N-type substrate (1); an N-type diffusion layer (2) on a light-receiving surface of the N-type substrate (1); a patterned first passivated contact structure (3) on the N-type diffusion layer (2), the patterned first passivated contact structure (3) comprising a first dielectric layer (31) having a thickness of less than or equal to 2 nm and an N-type doped polycrystalline silicon layer (32); and a second passivated contact structure (4) on a backside surface of the N-type substrate (1), the second passivated contact structure (4) comprising a second dielectric layer (41) having a thickness of greater than 2 nm and a P-type heavily doped polycrystalline silicon layer (42), a PN junction being formed on the backside surface, the second dielectric layer (41) having a through hole (411), and the doping concentration of the P-type heavily doped polycrystalline silicon layer (42) being 5×1018 to 3×1020 atoms / cm3. A first functional layer (5) and a first electrode (7) are sequentially provided on the N-type diffusion layer (2) and the first passivated contact structure (3), and a second functional layer (6) and a second electrode (8) are sequentially provided on the P-type heavily doped polycrystalline silicon layer (42).

The application discloses a kind of composite MOSFET photoelectric detectors based on mixed-dimensional material, belong to photoelectric detection field.The built-in electric field in the top PN junction of the detector makes a kind of photo-generated carrier be collected by graphene, so as to influence the junction carrier of bottom PN junction by high-k hexagonal boron nitride, and a MOSFET structure driven by light is formed;PbSe quantum dots expand the wavelength range of the device.The built-in electric field formed by bottom PN junction makes photo-generated carrier separate and produce intrinsic response;One-dimensional material can detect polarized light, and the cross-sectional area is small, effectively suppresses dark current.At the same time, the two PN junctions can be controlled by the top gate, so that the device works in the amplification zone of MOSFET, and the light response is linearly amplified.The application effectively avoids the occurrence of light gating, realizes polarization, wide band, high sensitivity, high-speed detector.

The invention provides a ceramic glaze composition, a preparation method of a semiconductor equipment part, the semiconductor equipment part and semiconductor equipment. The preparation method comprises the following steps: providing a first melting material, a second melting material and a semiconductor equipment part body; the first melting material comprises Al2O3, a corrosion-resistant additive and SiO2; the second melting material comprises SiO2, SiC and boride; respectively melting the first melting material and the second melting material, and uniformly mixing to obtain a ceramic glaze composition; applying a ceramic glaze composition to enable the ceramic glaze composition to at least cover part of the surface of the semiconductor equipment part body; and sintering to form a ceramic glaze layer on the surface of the semiconductor equipment part body. The mixed melting material is applied to the surface of the semiconductor equipment part body, and then the ceramic glaze layer is formed through high-temperature sintering, so that compared with a traditional anodic oxidation layer, the corrosion resistance is improved, the breakdown voltage resistance is improved, and the thermal cycle performance is also obviously improved.

The utility model discloses a kind of three-dimensional combined sealing structures of heterogeneous chip based on die attach film, it is related to the field of semiconductor packaging technology, including middle layer substrate, the double-sided integration RDL layer of middle layer substrate, and the position of middle layer substrate corresponding RDL layer is formed LCV copper via by laser drilling;The upper of middle layer substrate is respectively provided with display drive IC and touch sensor IC, and display drive IC and touch sensor IC are formed with micro copper column bump on the side close to middle layer substrate, the utility model, by adopting flexible polyimide substrate as the interlayer of carrier, double-sided rewiring, form micro via array by laser drilling, inner wall fills nano copper paste, LCV copper via is formed by low-temperature sintering;Upper chip is flip-chip soldered on die attach film circuit by micro copper column bump, interconnection is realized by the wiring on die attach film, and NCF is filled in the gap between upper chip and interlayer;Lower substrate pad is directly interconnected with die attach film circuit by LCV copper via.

The invention provides a superconducting quantum bit coupling structure, a superconducting quantum chip and a quantum computer, and relates to the technical field of quantum. The superconducting quantum bit coupling structure comprises a first superconducting quantum bit, a second superconducting quantum bit and a coupler, the first superconducting quantum bit is connected with a first node of the coupler through a first bypass capacitor, and the second superconducting quantum bit is connected with a second node of the coupler through a second bypass capacitor; the first Josephson junction and the third bypass capacitor of the coupler meet a target condition, so that when the magnetic flux in a first loop formed by the first Josephson junction, the second Josephson junction and the third Josephson junction of the coupler is 0, the coupling between the first superconducting quantum bit and the second superconducting quantum bit is closed. Therefore, the problem of crosstalk caused by short distance of the quantum bits in the prior art can be solved, coupling closing between the quantum bits when the magnetic flux is 0 is realized, and the precision requirement of magnetic flux regulation and control is reduced.

The invention relates to a semiconductor technology, in particular to a lateral varied doping P well region MOS (Metal Oxide Semiconductor) grid control thyristor and a manufacturing method thereof. On the basis of a traditional P well region MOS grid control thyristor structure, a P well region is changed to be formed by injecting P-type impurities into a plurality of windows at the same time and pushing junctions, and therefore the P well region variably doped in the transverse direction is formed. According to the structure, the transverse resistance of the P well region of the device is increased, the highest potential difference between the P well region and the N well region is increased during conduction, the conversion of the device from an IGBT conduction mode to a thyristor conduction mode is accelerated, and the conduction performance of the device is optimized only by regulating and controlling the size of a doping window while the complexity of the original process is kept unchanged.

To improve the uniformity of characteristics of a Josephson junction.SOLUTION: By depositing a superconducting material using the bridge structures 111 as a mask, the first superconductor layer 102 is formed on the substrate 101 so as to terminate at the first trailer 122 on one end side of the junction formation region 121. A first superconductor layer (102) is formed by depositing (vapor-depositing) a superconducting material on the surface of a substrate (101) from a direction at a first angle of less than 90 ° with respect to a vertical plane (132) on the surface of the substrate (101). After the first superconductor layer 102 is oxidized to form an insulating film, a superconducting material is deposited (vapor-deposited) on the surface of the substrate 101 from the direction of the second angle at which the absolute value of the difference between the second angle and 1 / 2 of the first angle is 45 ° with respect to the vertical plane 132, thereby forming the second superconductor layer 103 and forming a Josephson junction.SELECTED DRAWING: Figure 1D

Provided are a structure for reducing a SQUID superconducting loop area, and a preparation method therefor, wherein a stacked structure is formed on a silicon substrate, and precision etching is performed on the stacked structure, so that a 3D nano-bridge junction is formed on a sloped surface of the stacked structure and stretches across an insulating layer, such that batch preparation of the structure for reducing a SQUID superconducting loop area can be implemented, which facilitates large-scale application of SQUID probes. The plane of the 3D nano-bridge junction is perpendicular to the plane on which a SQUID superconducting loop is located, such that the width of the 3D nano-bridge junction no longer affects a SQUID effective loop area, so that the thickness of the 3D nano-bridge junction can be individually regulated in order to improve SQUID performance, which significantly weakens the inhibition effect of a magnetic field on the superconducting characteristics of the 3D nano-bridge junction. In addition, the SQUID superconducting loop having a minimum line width of 10nm can be prepared in combination with an electron beam lithography technique having higher precision, significantly reducing the SQUID superconducting loop area, improving spin sensitivity, and thereby achieving higher spatial resolution during scanning magnetic imaging.

The utility model relates to the technical field of semiconductor devices, and provides a groove type silicon carbide MOSFET device. The device comprises a substrate, an epitaxial layer and a polycrystalline silicon gate. The epitaxial layer includes a bottom screen junction and a side screen junction. The bottoms of the side screen knots are connected with the bottom screen knots in a staggered mode to form grid staggering. The epitaxial layer is provided with a groove, the connecting position of the side wall and the bottom of the groove is in an arc shape, the bottom of the groove is sunken in the bottom screen junction, and the groove is located between the side screen junctions. Through the three-dimensional grid shielding system formed by the bottom screen junction and the side screen junction, surrounding type shielding can be formed on the polycrystalline silicon gate region below the bottom and the side wall of the groove, the peak electric field intensity borne by the polycrystalline silicon gate oxide layer under high voltage is dispersed and reduced to the maximum extent, and the voltage endurance capability and the gate oxide reliability of the device are remarkably improved.

A semiconductor chip being a transient voltage suppressor (TVS) diode includes: a first pin junction part and a second pin junction part which are in a first polarity direction; and a diode pair region which, when viewed in plan view, is provided spaced apart from both the first pin junction part and the second pin junction part. The diode pair region includes: a first reverse pin junction part and a second reverse pin junction part which are in a second polarity direction; and a pn junction part in the first polarity direction, which, when viewed in plan view, is provided at a position overlapping the first reverse pin junction part and the second reverse pin junction part and which constitutes the first reverse pin junction part, the second reverse pin junction part and a diode pair. When viewed in plan view, the diode pair region is arranged between the first pin junction part and the second pin junction part.

A photovoltaic power converter (1N) suitable for use in implanted AIMD's is provided which comprises an insulating substrate (5s) supporting N photovoltaic cells (= PV-cell) (1.1-1.N) physically separated from one another by gaps and conductively coupled in series to one another, wherein N ≥ 2. A blocking layer (4b) is interposed between each of the N PV-cells and the insulating substrate (5s) to reduce photo-leakage caused by photoconductivity of the insulating substrate (5s). Each blocking layer (4b) is formed by M blocking PN-junctions, wherein M ≥ N + 1, each formed between a pair of first and second type p and type n semiconductors (4pi, 4ni, with i = 1 to M), wherein the first blocking PN-junction located closest to the photovoltaic PN-junction has a second polarity of opposite sign from the polarity of the PN junction of the PV cell.

To improve electrical characteristics of a TVS diode.SOLUTION: A semiconductor chip 20 of a TVS diode 10 includes a first pin junction part 30 in a first polarity direction and a diode pair region 60. The diode pair region 60 includes: a first inverse pin junction part 60A in a second polarity direction which is provided while being separated from the first pin junction part 30 in a planar view; and a pn junction part 60E in the first polarity direction constituting a diode pair with the first inverse pin junction part 60A. The first pin junction part 30 includes: a p-type first terminal side high concentration region 31; an n-type first terminal side low concentration region 32 provided at a position overlapping the first terminal side high concentration region 31 in the planar view; an n-type first terminal side contact region 33; and a p-type first buffer region 35 in contact with the first terminal side high concentration region 31 between the first terminal side high concentration region 31 and the first terminal side low concentration region 32 in a thickness direction of the semiconductor chip 20.SELECTED DRAWING: Figure 29

The invention discloses a solar cell and a preparation method thereof, and a photovoltaic module. The solar cell comprises a silicon substrate, and the silicon substrate is provided with a first region and a second region; the patterned PN junction is arranged on the first region of the silicon substrate, and the patterned PN junction is arranged in a convex manner relative to the surface of the silicon substrate in the second region; and the first electrode is in ohmic contact with the patterned PN junction. According to the invention, carrier recombination in the PN junction can be effectively inhibited, and the photoelectric conversion efficiency of the solar cell is improved.

The application discloses a packaging method and a packaged superconducting quantum chip. The packaging method comprises the following steps: providing a first substrate and a second substrate; preparing a first superconducting metal pattern and a Josephson junction on the one side surface of the first substrate in sequence to form a superconducting quantum chip; wherein the first superconducting metal pattern comprises a first transmission line, a first pad, a first electrode and a second electrode; the Josephson junction is located between the first electrode and the second electrode and is electrically connected with the first electrode and the second electrode to form a quantum bit; preparing a second superconducting metal pattern on the one side surface of the second substrate to form a packaging substrate; and aligning and welding the first pad and the second pad by using a flip-chip process to package the superconducting quantum chip by using the packaging substrate. By using the method, the superconducting quantum chip is packaged by using a superconducting packaging substrate, energy dissipation is reduced, the performance and heat conductivity of the superconducting quantum chip are improved, the superconducting quantum chip is easy to integrate, and the cost is low.

The application relates to the field effect transistor technology field and discloses a semiconductor field effect transistor capable of completely eliminating the substrate auxiliary depletion effect, which comprises a P-type substrate, a super junction above the P-type substrate, an N-type buffer layer above the right side of the P-type substrate, a drain N heavy doping area above the right side of the N-type buffer layer, the drain N heavy doping area enabling the drain electrode to form an ohmic contact with the N-type buffer layer and the super junction comprising super junction P columns and super junction N columns, a P-type heavy doping area above the left side of the P-type substrate, a P well formed on the right side of the P-type heavy doping area, a source N heavy doping area formed in the P well, and the source electrode, the gate electrode and the drain electrode being distributed on the upper surface of the whole device. The application makes the surface electric field distribution of the substrate and the super junction consistent, eliminates the adverse effect of the substrate auxiliary depletion effect, improves the conduction characteristics of the device, increases the breakdown voltage of the device, effectively reduces the leakage current from the super junction to the substrate, and makes the device closer to the theoretical limit of the ideal super junction.

A method of the subject technology includes creating a dark finish coating on charging contacts of a device by reducing Schottky junctions at an interface of a metal substrate and the dark finish coating, as well as between the charging contacts of device and charger. The Schottky junctions are formed at a semiconductor-metal interface and reducing the Schottky junction is accomplished through co-deposition during a physical vapor deposition (PVD) process.

The invention discloses a rotary rectification chip and a production method, relates to the field of chip production, and covers the whole process from substrate layer preparation, PN junction formation, metal electrode manufacturing, passivation protection, wafer thinning and cutting to final chip testing and sorting. In the chip testing and sorting link, an advanced yield management and fault diagnosis mechanism is integrated. According to the method, visual inspection and experience judgment are no longer performed on the wafer graph only by manual work, the test result is intelligently analyzed, especially when the wafer yield is lower than the preset threshold value, the wafer graph image matrix can be automatically constructed, and pattern recognition and attribution of the yield spatial distribution graph are performed based on the wafer graph image matrix. The data-driven analysis mode can efficiently and objectively identify the failure point with the specific spatial pattern, so that the production efficiency and the product yield of the rotary rectification chip are remarkably improved.

This invention provides a superconducting quantum interference device (SQUID) based on a Josephson junction and its fabrication method. By improving the fabrication process of the Josephson junction, an organic cleaning process is added during the photoresist stripping process, which allows the sidewalls formed by continuous stacking to be removed, improving the quality of the subsequently deposited thin film. This makes the SQUID output curve less prone to resonance and improves the yield of the SQUID mass production process. Based on the traditional SQUID, this invention adds an additional Josephson junction in series or parallel to each Josephson junction to form a SQUID with four Josephson junctions, thereby obtaining a larger output voltage modulation depth. This results in higher sensitivity, lower noise, and a larger linear range for the SQUID, making the circuit less prone to lockout. It also eliminates the need for lengthy bias lines and avoids problems such as magnetic flux crosstalk and poor magnetic flux coherence, making the layout design simpler and more convenient.