24 results about "Junction formation" patented technology

The application discloses a method for realizing an integrated ultrahigh-temperature environmental barrier composite coating. After a high-entropy alloy or boride layer and a molybdenum metal pre-coating layer are pre-coated on the surface of a substrate, a silicon-boron co-embedding deposition is carried out through a pre-oxidation process to form an ordered Mo-Si-B multilayer structure in the molybdenum metal layer. A composite coating formed by a metal silicide and silicon dioxide is cold sprayed on the Mo-Si-B multilayer structure to form a three-dimensional network structure composite self-healing layer through high-temperature sintering. An alloy oxide is cold sprayed or magnetron sputtered outside the composite self-healing layer to form a water vapor resistant layer. Through the integrated coating preparation process, the advantages of different components are complementary, and the effective protection of various refractory alloys in a wide temperature range (room temperature-1700 DEG C) can be realized.

According to the silicon-based PIN photodiode, the manufacturing method and the electronic device provided by the invention, the FZ single crystal is adopted as the substrate, and the doped region is formed in an ion implantation and annealing mode, so that the junction depth and the concentration can be effectively controlled. And thinning the silicon wafer by adopting a Taiko back thinning process. The photosensitive area adopts a shallow junction and deep junction combined structure, the shallow junction can increase the blue light absorption rate, and the deep junction forms ohmic contact. The anti-reflection layer adopts a silicon dioxide and silicon nitride double-layer structure, so that the surface stress of silicon / silicon nitride can be effectively relieved, and the reliability is improved. The cut-off region N + and the back N + can reduce dark current, and back metallization can form a back cathode.

Methods and structures are presented for mitigating back-gating effects in radio frequency (RF) silicon-on-insulator (SOI) substrates, RF-SOI. According to an aspect, a first implant or junction is formed in a region of a trap-rich layer (TRL) of the RF-SOI beneath a first circuit / device to be protected. The first implant or junction is entirely contained within the TRL. A planar surface area of the first implant and / or junction entirely contains a projection of a planar surface area of the first circuit and / or device. The first implant or junction is biased via a through-BOX contact (TBC) that penetrates a BOX layer at a shallow trench isolation region formed in the RF-SOI. According to another aspect, a second implant or junction is formed in a region of the TRL beneath a second circuit / device. The first implant or junction and the second implant or junction are not connected and are separated by an undoped region of the TRL.

Approaches herein provide devices, systems, and methods of transistor patterning using a frontside implant plus epitaxial process to form a graded junction having a high surface doping concentration for a vertical contact transistor bitline. One method may include delivering ions into a front side of a substrate of a transistor to form a graded junction in the substrate, wherein the substrate is maintained at a temperature greater than 100° C. while the ions are delivered into the substrate, and thermally treating the graded junction. The method may further include forming, after the graded junction is thermally treated, an epitaxial layer over the graded junction, forming a plurality of gates in the epitaxial layer, and processing a backside of the substrate to remove the substrate to the graded junction following formation of the plurality of gates.

The application provides a vertical semiconductor structure with integrated sampling structure and a manufacturing method thereof. The vertical semiconductor structure with integrated sampling structure comprises a vertical semiconductor structure cell, a sampling cell, a control electrode, a first electrode, a second electrode and a sampling electrode. According to an embodiment of the application, firstly, the sampling electrode can sample the voltage difference between the first electrode and the second electrode in real time; a PN junction is formed between the first / two P-type diffusion regions and the second N-type base region of the sampling cell, and the PN junction forms a potential barrier for blocking the electron emission of the sampling electrode, so that the voltage signal of the sampling electrode is input to a protection circuit, and the protection circuit can safely and quickly detect whether the vertical semiconductor structure is in a desaturation state when judging that the vertical semiconductor structure cell is in an open state. Secondly, a sampling resistor is connected in series between the sampling electrode and the first electrode, and the positive voltage of the sampling electrode can increase the height of the potential barrier, so as to ensure the stable work of the sampling cell.

A semiconductor device includes a device region, including a source contact, a drain contact formed on a substrate, and a gate contact formed between the source contact and the drain contact; an isolation region surrounding the device region, the isolation region including an N-type semiconductor region formed on the substrate, a first silicide layer and a second silicide layer formed in the N-type semiconductor region and separated from each other by an isolation layer, and an anode contact and a cathode contact connected to the first silicide layer and the second silicide layer, respectively; and a Schottky barrier diode formed inside the isolation region by a junction of the first silicide layer and the N-type semiconductor region. The anode contact is connected to the source contact, and the cathode contact is connected to the drain contact.

One or more gated nanosheet diodes are disposed on a substrate and made from a nanosheet structure. A first (second) source / drain (S / D) is disposed on the substrate. The first (second) S / D has a first (second) S / D doping concentration of a first (second) S / D doping type. One or more p-n junctions form one or more respective diodes. Each of the p-n junctions has a first side and a second side. The first (second) side of the p-n junction is electrically and physically connected to the first (second) S / D and has a same type of doping, respectively. A gate stack made from a gate dielectric layer and a gate metal interfaces and surrounds each of the p-n junctions.

Provided in the present application are a solar cell, a manufacturing method therefor and a photovoltaic module. The solar cell comprises: an N-type substrate (1); an N-type diffusion layer (2) on a light-receiving surface of the N-type substrate (1); a patterned first passivated contact structure (3) on the N-type diffusion layer (2), the patterned first passivated contact structure (3) comprising a first dielectric layer (31) having a thickness of less than or equal to 2 nm and an N-type doped polycrystalline silicon layer (32); and a second passivated contact structure (4) on a backside surface of the N-type substrate (1), the second passivated contact structure (4) comprising a second dielectric layer (41) having a thickness of greater than 2 nm and a P-type heavily doped polycrystalline silicon layer (42), a PN junction being formed on the backside surface, the second dielectric layer (41) having a through hole (411), and the doping concentration of the P-type heavily doped polycrystalline silicon layer (42) being 5×1018 to 3×1020 atoms / cm3. A first functional layer (5) and a first electrode (7) are sequentially provided on the N-type diffusion layer (2) and the first passivated contact structure (3), and a second functional layer (6) and a second electrode (8) are sequentially provided on the P-type heavily doped polycrystalline silicon layer (42).

The invention provides a ceramic glaze composition, a preparation method of a semiconductor equipment part, the semiconductor equipment part and semiconductor equipment. The preparation method comprises the following steps: providing a first melting material, a second melting material and a semiconductor equipment part body; the first melting material comprises Al2O3, a corrosion-resistant additive and SiO2; the second melting material comprises SiO2, SiC and boride; respectively melting the first melting material and the second melting material, and uniformly mixing to obtain a ceramic glaze composition; applying a ceramic glaze composition to enable the ceramic glaze composition to at least cover part of the surface of the semiconductor equipment part body; and sintering to form a ceramic glaze layer on the surface of the semiconductor equipment part body. The mixed melting material is applied to the surface of the semiconductor equipment part body, and then the ceramic glaze layer is formed through high-temperature sintering, so that compared with a traditional anodic oxidation layer, the corrosion resistance is improved, the breakdown voltage resistance is improved, and the thermal cycle performance is also obviously improved.

The utility model discloses a kind of three-dimensional combined sealing structures of heterogeneous chip based on die attach film, it is related to the field of semiconductor packaging technology, including middle layer substrate, the double-sided integration RDL layer of middle layer substrate, and the position of middle layer substrate corresponding RDL layer is formed LCV copper via by laser drilling;The upper of middle layer substrate is respectively provided with display drive IC and touch sensor IC, and display drive IC and touch sensor IC are formed with micro copper column bump on the side close to middle layer substrate, the utility model, by adopting flexible polyimide substrate as the interlayer of carrier, double-sided rewiring, form micro via array by laser drilling, inner wall fills nano copper paste, LCV copper via is formed by low-temperature sintering;Upper chip is flip-chip soldered on die attach film circuit by micro copper column bump, interconnection is realized by the wiring on die attach film, and NCF is filled in the gap between upper chip and interlayer;Lower substrate pad is directly interconnected with die attach film circuit by LCV copper via.

The invention provides a superconducting quantum bit coupling structure, a superconducting quantum chip and a quantum computer, and relates to the technical field of quantum. The superconducting quantum bit coupling structure comprises a first superconducting quantum bit, a second superconducting quantum bit and a coupler, the first superconducting quantum bit is connected with a first node of the coupler through a first bypass capacitor, and the second superconducting quantum bit is connected with a second node of the coupler through a second bypass capacitor; the first Josephson junction and the third bypass capacitor of the coupler meet a target condition, so that when the magnetic flux in a first loop formed by the first Josephson junction, the second Josephson junction and the third Josephson junction of the coupler is 0, the coupling between the first superconducting quantum bit and the second superconducting quantum bit is closed. Therefore, the problem of crosstalk caused by short distance of the quantum bits in the prior art can be solved, coupling closing between the quantum bits when the magnetic flux is 0 is realized, and the precision requirement of magnetic flux regulation and control is reduced.

To improve the uniformity of characteristics of a Josephson junction.SOLUTION: By depositing a superconducting material using the bridge structures 111 as a mask, the first superconductor layer 102 is formed on the substrate 101 so as to terminate at the first trailer 122 on one end side of the junction formation region 121. A first superconductor layer (102) is formed by depositing (vapor-depositing) a superconducting material on the surface of a substrate (101) from a direction at a first angle of less than 90 ° with respect to a vertical plane (132) on the surface of the substrate (101). After the first superconductor layer 102 is oxidized to form an insulating film, a superconducting material is deposited (vapor-deposited) on the surface of the substrate 101 from the direction of the second angle at which the absolute value of the difference between the second angle and 1 / 2 of the first angle is 45 ° with respect to the vertical plane 132, thereby forming the second superconductor layer 103 and forming a Josephson junction.SELECTED DRAWING: Figure 1D

Provided are a structure for reducing a SQUID superconducting loop area, and a preparation method therefor, wherein a stacked structure is formed on a silicon substrate, and precision etching is performed on the stacked structure, so that a 3D nano-bridge junction is formed on a sloped surface of the stacked structure and stretches across an insulating layer, such that batch preparation of the structure for reducing a SQUID superconducting loop area can be implemented, which facilitates large-scale application of SQUID probes. The plane of the 3D nano-bridge junction is perpendicular to the plane on which a SQUID superconducting loop is located, such that the width of the 3D nano-bridge junction no longer affects a SQUID effective loop area, so that the thickness of the 3D nano-bridge junction can be individually regulated in order to improve SQUID performance, which significantly weakens the inhibition effect of a magnetic field on the superconducting characteristics of the 3D nano-bridge junction. In addition, the SQUID superconducting loop having a minimum line width of 10nm can be prepared in combination with an electron beam lithography technique having higher precision, significantly reducing the SQUID superconducting loop area, improving spin sensitivity, and thereby achieving higher spatial resolution during scanning magnetic imaging.

The utility model relates to the technical field of semiconductor devices, and provides a groove type silicon carbide MOSFET device. The device comprises a substrate, an epitaxial layer and a polycrystalline silicon gate. The epitaxial layer includes a bottom screen junction and a side screen junction. The bottoms of the side screen knots are connected with the bottom screen knots in a staggered mode to form grid staggering. The epitaxial layer is provided with a groove, the connecting position of the side wall and the bottom of the groove is in an arc shape, the bottom of the groove is sunken in the bottom screen junction, and the groove is located between the side screen junctions. Through the three-dimensional grid shielding system formed by the bottom screen junction and the side screen junction, surrounding type shielding can be formed on the polycrystalline silicon gate region below the bottom and the side wall of the groove, the peak electric field intensity borne by the polycrystalline silicon gate oxide layer under high voltage is dispersed and reduced to the maximum extent, and the voltage endurance capability and the gate oxide reliability of the device are remarkably improved.

A photovoltaic power converter (1N) suitable for use in implanted AIMD's is provided which comprises an insulating substrate (5s) supporting N photovoltaic cells (= PV-cell) (1.1-1.N) physically separated from one another by gaps and conductively coupled in series to one another, wherein N ≥ 2. A blocking layer (4b) is interposed between each of the N PV-cells and the insulating substrate (5s) to reduce photo-leakage caused by photoconductivity of the insulating substrate (5s). Each blocking layer (4b) is formed by M blocking PN-junctions, wherein M ≥ N + 1, each formed between a pair of first and second type p and type n semiconductors (4pi, 4ni, with i = 1 to M), wherein the first blocking PN-junction located closest to the photovoltaic PN-junction has a second polarity of opposite sign from the polarity of the PN junction of the PV cell.

The invention discloses a solar cell and a preparation method thereof, and a photovoltaic module. The solar cell comprises a silicon substrate, and the silicon substrate is provided with a first region and a second region; the patterned PN junction is arranged on the first region of the silicon substrate, and the patterned PN junction is arranged in a convex manner relative to the surface of the silicon substrate in the second region; and the first electrode is in ohmic contact with the patterned PN junction. According to the invention, carrier recombination in the PN junction can be effectively inhibited, and the photoelectric conversion efficiency of the solar cell is improved.

The application discloses a packaging method and a packaged superconducting quantum chip. The packaging method comprises the following steps: providing a first substrate and a second substrate; preparing a first superconducting metal pattern and a Josephson junction on the one side surface of the first substrate in sequence to form a superconducting quantum chip; wherein the first superconducting metal pattern comprises a first transmission line, a first pad, a first electrode and a second electrode; the Josephson junction is located between the first electrode and the second electrode and is electrically connected with the first electrode and the second electrode to form a quantum bit; preparing a second superconducting metal pattern on the one side surface of the second substrate to form a packaging substrate; and aligning and welding the first pad and the second pad by using a flip-chip process to package the superconducting quantum chip by using the packaging substrate. By using the method, the superconducting quantum chip is packaged by using a superconducting packaging substrate, energy dissipation is reduced, the performance and heat conductivity of the superconducting quantum chip are improved, the superconducting quantum chip is easy to integrate, and the cost is low.

A method of the subject technology includes creating a dark finish coating on charging contacts of a device by reducing Schottky junctions at an interface of a metal substrate and the dark finish coating, as well as between the charging contacts of device and charger. The Schottky junctions are formed at a semiconductor-metal interface and reducing the Schottky junction is accomplished through co-deposition during a physical vapor deposition (PVD) process.

The invention discloses preparation and application of a Schottky coupling homojunction semiconductor material, and belongs to the technical field of semiconductor materials.The preparation method of the Schottky coupling homojunction semiconductor material comprises the following steps that a CdS nanorod is synthesized through a hydrothermal method, then, CdS quantum dots are synthesized on the CdS nanorods in situ through a hydrothermal method, so that CdS homojunctions are obtained, and finally, the gold nanoparticles are coupled with the CdS homojunctions. According to the invention, the S-type homojunction and the Schottky junction are innovatively combined to form a synergistic effect of'efficient separation + plasma amplification ', and the signal leap-type promotion is realized, so that the self-powered photoelectrochemical sensor prepared based on the material has higher detection sensitivity and has great potential in the development of portable sensing equipment.

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of first forming a spin orbit torque (SOT) layer on a substrate, forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first cap layer adjacent to the MTJ, and then forming a second cap layer adjacent to the first cap layer. Preferably, a top surface of the second cap layer is lower than a top surface of the first cap layer.

This invention provides a method for detecting the distribution of COP-free regions in silicon single crystals, relating to the field of silicon single crystal quality testing technology. The method includes: cleaning a silicon wafer to be tested to obtain a first silicon wafer; uniformly coating the surface of the first silicon wafer with a transition metal ion solution to obtain a second silicon wafer; placing the second silicon wafer in a high-temperature environment and performing heat treatment at three temperature gradients to obtain a third silicon wafer; wherein in a first stage, transition metal ions diffuse to the surface of the silicon wafer to activate oxygen precipitates in the Pv region; in a second stage, transition metal ions are promoted to diffuse into the interior of the silicon wafer to develop the low-oxygen Pi region; and in a third stage, high-temperature activation of atomic nuclei aggregation in the B-band region to form differentially spaced rings; cleaning the third silicon wafer with a mixed acid solution to obtain a fourth silicon wafer; placing the fourth silicon wafer in a selective etching solution for selective etching; and detecting the distribution of COP-free regions on the obtained test sample. This method can improve the clarity of the boundaries of each region, thereby improving the accuracy of COP-free region distribution detection.

The application provides a kind of LDMOS structure and manufacturing method based on in-vivo curvature extension, comprising: first conductive type semiconductor substrate, second conductive type drift region, first conductive type well region, first conductive type buried layer and second conductive type buried layer formed by ion implantation after grooving and high-temperature push joint, polysilicon gate electrode located on the surface of the device, first dielectric oxide layer, second dielectric oxide layer, third dielectric oxide layer, first conductive type buried layer and second conductive type buried layer are located in the substrate, and the grooving is filled with dielectric; the first conductive type buried layer and the second conductive type buried layer are introduced into the substrate, a larger curvature is formed in the body of the device, the electric field distribution in the body of the device is optimized, the distance of the drift region can be shortened, and the lateral withstand voltage problem of the device is solved.

The invention relates to a Cu3SbSe3 alloyed p-type Bi2Te3-based thermoelectric material and a preparation method of a device of the Cu3SbSe3 alloyed p-type Bi2Te3-based thermoelectric material. The preparation method comprises the following steps: weighing Bi, Sb and Te raw materials according to a set molar ratio, adding Cu3SbSe powder, mixing, and carrying out vacuum packaging, high-temperature melting and slow cooling to obtain an alloy ingot; and then performing high-energy ball milling to obtain powder with uniform particle size, and performing rapid hot pressed sintering to form a high-density block material. The obtained material is complete in crystal structure, uniform in structure, high in power factor and low in lattice thermal conductivity, and the thermoelectric figure of merit zT of the material at 378 K is increased by about 20% compared with that of a base material and can reach 1.45 to the maximum. The maximum output power of a plurality of pairs of p-n supporting leg thermoelectric devices prepared from the material is 0.19 W under the temperature difference of 182 K, and the maximum energy conversion efficiency is 6.9%. The method is simple and convenient in process, good in repeatability and suitable for large-scale preparation of high-performance Bi2Te3-based thermoelectric materials and efficient thermoelectric devices.

Methods and structures for mitigating back-gate effects in a radio frequency (RF) silicon-on-insulator (SOI) substrate, RF-SOI, are presented. According to one aspect, a first implant or junction is formed in a region of a trap-rich layer (TRL) of the RF-SOI that is located below a first circuit / device to protect. The first implant or junction is fully contained within the TRL. A planar surface area of the first implant and / or junction fully contains a projection of a planar surface area of the first circuit and / or device. The first implant or junction is biased via a through BOX contact (TBC) that penetrates the BOX layer at a shallow trench isolation region formed in the RF-SOI. According to another aspect, a second implant or junction is formed in a region of the TRL below a second circuit / device. The first and second implants or junctions are disjoint and separated by an undoped region of the TRL.