126 results about "Junction formation" patented technology

A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications.

A system and method are provided which enable the joining of two materials via ultrasonic welding, including materials normally considered incompatible in traditional ultrasonic welding techniques. The system permits ultrasonic welding of a first material to a second material, the second material including material types normally considered incompatible with the first material and includes an abrader for altering the surface of the material/s to be joined. A first pressure device is operative to vary the position of the abrader and thereby vary the abrasion applied to the materials. An ultrasonic source provides acoustic energy to a weld interface between the materials. A second pressure device is operative to vary the force applied to the interface between the materials while a sensor senses the weld interface temperature. A controller dynamically adjusts the acoustic energy of the ultrasonic source, the second pressure device, and at least one of the first pressure device and a temperature varying device during junction formation. The temperature varying device is operative to modify the temperature of the material/s being welded before abrasion and/or proximate the weld interface location. In this manner, the system enables a smooth, continuous junction to form at a predetermined rate.

Embodiments of the present invention may include an improved thin film solar cell device that is formed by sequentially depositing an intrinsic amorphous silicon layer and an intrinsic microcrystalline silicon layer during the p-i-n or n-i-p junction formation process. Embodiments of the invention also generally provide a method and apparatus for forming the same. The present invention may be used to advantage to form other single junction, tandem junction, or multi-junction thin film solar cell devices.

The invention relates to a non-equilibrium junction terminal architecture for a super-junction device. The junction terminal region of the terminal structure is provided with a plurality of uniform P pillars with different doping concentrations; the effective ion implantation area of the P pillars is correspondingly adjusted on the layout design according to the transverse electric field distribution conditions of all positions, so that the P pillars are completely exhausted when achieving the breakdown voltage; the ions are simultaneously implanted into all the P pillars under the masking of the mask sheet, thereby controlling the total amount of acceptor ions of all the P pillars in the junction terminal region; and after carrying out multiple extensions and multiple ion implantation processes, long-time high-temperature junction push is carried out to form several uniform P pillars with different doping concentrations. The invention can effectively improve the breakdown voltage characteristics of the junction terminal device, and has smaller junction terminal length, so that the total area of the device is reduced, thereby reducing the device conduction resistance on the same chip area.

The invention relates to an SOI base-based low-leakage and low-capacitance TVS array and a preparation method thereof. The SOI base-based low-leakage and low-capacitance TVS array comprises an n-type SOI base, a p+ region, an n+ region, a p region, a silicon nitride isolator and an electrode, wherein the n-type SOI base is formed by a three-layer structure of an Si substrate, an SiO<2> layer and an n-type Si layer; and highly doped PN junctions are formed on P-type and/N-type SI substrates through diffusion or ion implantation to form a PN junction region and a central TVS region. Compared with a TVS device in the prior art, according to the SOI base-based low-leakage and low-capacitance TVS array, the stray capacitance and the leakage current of the device are effectively reduced; the power consumption of the device is reduced; and the performance of the device is further improved.

The invention discloses a preparation method of a P-type crystal silicon double-sided cell. The preparation method comprises the following steps of felting and chemical cleaning, PN junction formation, antireflection film deposition performed on two sides, film splitting performed on a back surface, cell positive and negative pole preparation and sintering. Compared with the prior art, and according to the preparation method of the P-type crystal silicon double-sided cell of the invention, only one-time doping is required, and therefore, a preparation process can be simpler; and original processes such as frequent high-temperature doping and mask manufacture can be avoided, and therefore, preparation steps can be simplified, and preparation cost can be saved. The double-sided cell prepared by using the preparation method provided by the technical schemes of the invention can fully utilize scattered light of sunlight on the ground, and therefore, the utilization rate of the sunlight can be improved, power generation amount of the cell can be increased.

The invention discloses a heterojunction solar cell and an interfacing processing method and preparing technology thereof. According to the interface processing method of the heterojunction solar cell, in the preparing technology of the heterojunction solar cell, highly doping processing is conducted on the front surface of a crystalline silicon wafer with the ion implantation technology or the diffusion technology so that a heavy doped layer can be formed on the front surface of the crystalline silicon wafer, and then the Fermi level of the surface of the crystalline silicon water of the heterojunction solar cell is changed and an built-in electric field is enhanced. According to the method, the built-in electric field of the substrate interface of crystalline silicon can be enhanced, separation and conveyance of current carriers on the border of a depletion region can be promoted more effectively, film/crystalline silicon abrupt junction formation is facilitated, the width of a depletion layer on the base region of the crystalline silicone is reduced, light absorption efficiency is improved, recombination losses of the current carriers are reduced, and the voltage characteristic of a heterojunction efficient battery is improved.

A MOSFET and the method for fabricating them are disclosed to make the inkjet head chips. The MOSFET has the scaled-down junction formation for the source and drain. Using a lower temperature process and interlayer dielectric, the source and drain dopants can not be diffused deeply due to high-temperature driver-in. The contact holes of the drain are provided with plugs of refractory material to avoid spiking between the metal and silicon. This achieves the requirement of high-density devices on the print head chip.

Provided are a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes an isolation insulating film, an epitaxial silicon layer, a junction blocking insulating film, a gate stack, and source and drain junctions. The isolation insulating film is formed on a semiconductor substrate to define an active area. The epitaxial silicon layer is formed in the active area of the semiconductor substrate and surrounded by the isolation insulating film. The junction blocking insulating film is formed in the epitaxial silicon layer. The gate stack is formed over the epitaxial silicon layer so that the junction blocking insulating film is buried under approximately the center of the gate stack. The source and drain junctions are formed adjacent the sidewalls of the gate stack. Accordingly, a short circuit between source/drain junctions in a bulk area caused by the unwanted diffusion of the junctions can be prevented.

An embodiment of the invention discloses a high-density and embedded-type capacitor and a manufacturing method of the high density and embedded-type capacitor. The method comprises providing a base with a body layer and an etching barrier layer, forming a plurality of grooves with good verticality and high depth-to-width ratios, doping body layer materials of the bottom side walls of the groove and body layer materials between adjacent groove to get a doping area of the capacitor in order to form a three-dimensional PN junction on the contact regions of the body layer and a doping region, and forming a first electrode and a second electrode of the capacitor, wherein the polarities of the first electrode and the second electrode are opposite, and are electrically insulated, the first electrode is placed on two sides of the doping area or the periphery of the doping area, and the second electrode is placed on the surface of the doping area. Because the dielectric layer of the capacitor is made of three-dimensional grooves, the effective area of the dielectric layer is much larger than of a dielectric layer of an ordinary capacitor. Therefore, capacitance density of the capacitor is improved, and the capacitor can simultaneously satisfy requirements of low frequency decoupling and high frequency decoupling.

A method of forming a semiconductor device is disclosed including providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, and forming a transistor device on the silicon-on-insulator substrate including providing a gate structure on the semiconductor layer having a gate electrode and a first cap layer on the gate electrode, growing an oxide liner on the transistor device having a first part covering the gate structure and a second part covering the semiconductor layer, forming a second cap layer on the oxide liner, at least partially removing the second part of the oxide liner underneath the second cap layer and the first part of the oxide liner, and epitaxially forming raised source/drain regions on the semiconductor layer.

The present invention relates to an inductive dipole element for a superconducting microwave quantum circuit. The dipole element comprises a DC-SQUID formed by a pair of Josephson junctions shunted by an inductance, wherein the Josephson junctions have equal energy, and the Josephson junctions and the inductance are arranged such that each of the junctions forms a loop with the inductance. The two loops are asymmetrically threaded with external magnetic DC fluxes φ_ext1 and φ_ext2, respectively, such that φ_ext1=π and φ_ext2=0, wherein parametric pumping is enabled by modulating the total flux φ_Σ=φ_ext,1+φ_ext,2 threading the dipole element, thereby allowing even-wave mixing between modes that participate in the dipole element with no Kerr-like interactions.

The invention discloses a germanium-silicon HBT (Heterojunction Bipolar Transistor) device with a spuriously buried layer. The device comprises a collector region, an N-type spuriously buried layer, an intrinsic base region, an outer base region and an emitting region, wherein the collector region comprises a first N-type ion injection region formed between shallow slots, and a second N-type ion injection region formed in the first N-type ion injection region; the N-type spuriously buried layer is formed at the bottoms of the shallow slots positioned on the both sides of an active region, and metal silicide is formed on the contact parts of the N-type spuriously buried layer and the shallow slots; the intrinsic base region comprises a germanium-silicon epitaxial layer; the outer base region comprises polysilicon of the outer base region and metal silicide, the polysilicon of the outer base region is formed on the upper parts of the shallow slots and contacts the intrinsic base region, and the metal silicide is positioned on the upper part of the polysilicon of the outer base region and contacts the polysilicon of the outer base region; and the emitting region comprises N-type emitting electrode polysilicon which is formed on the upper part of the intrinsic base region and contacts the intrinsic base region. The invention also discloses a manufacturing method of the device. The germanium-silicon HBT device disclosed by the invention shortens transition time of a base region and an exhaust region formed by a junction of the base region and the collector region so as to improve the working cut-off frequency of the device, prevents generation of silicon oxides through the metal silicide with deep contact holes, and reduces the open-circuit risk of a circuit so as to improve the reliability of the device.

A method of forming a diffusion region is disclosed. The method includes depositing a nanoparticle ink on a surface of a wafer to form a non-densified thin film, the nanoparticle ink having set of nanoparticles, wherein at least some nanoparticles of the set of nanoparticles include dopant atoms therein. The method also includes heating the non-densified thin film to a first temperature and for afirst time period to remove a solvent from the deposited nanoparticle ink; and heating the non-densified thin film to a second temperature and for a second time period to form a densified thin film, wherein at least some of the dopant atoms diffuse into the wafer to form the diffusion region.

TSV devices with p-n junctions that are planar have superior performance in breakdown and current handling. Junction diode assembly formed in enclosed trenches occupies less chip area compared with junction-isolation diode assembly in the known art. Diode assembly fabricated with trenches formed after the junction formation reduces fabrication cost and masking steps increase process flexibility and enable asymmetrical TSV and uni-directional TSV functions.