4results about How to "Improved breakdown voltage characteristics" patented technology

The present application relates to a GaN HEMT power semiconductor epitaxial wafer, comprising: a silicon (Si) substrate; a nucleation region formed on the substrate; a stress relief region formed on the nucleation region; a buffer region formed on the stress relief region; a channel region formed on the buffer region; and a barrier region formed on the channel region. Wherein, below the channel region, specifically, at any position between the buffer region and the channel region, inside the buffer region, or between the stress relief region and the buffer region, a rear barrier region is provided. The rear barrier region has a superlattice structure or a multilayer structure in which layers of 2H-Al(Ga)N material and layers of 4H-SiC(N) material are alternately stacked.

The invention discloses a power semiconductor device and a preparation method thereof. The power semiconductor device comprises a substrate, and the substrate comprises a substrate and an epitaxial layer located on the substrate; a plurality of first cells and second cells, wherein the first cells and the second cells are arranged in parallel in the first direction; the second cell comprises communication grooves penetrating from the surface of the epitaxial layer to the interior of the epitaxial layer, the communication grooves comprise second grooves and third grooves, and the third grooves are located between the adjacent second grooves and are communicated with the adjacent second grooves; the well regions are located in the epitaxial layer, the well regions extend into the epitaxial layer from the surface of the epitaxial layer, and the well regions are located on the two sides of the communicating groove; the second cell comprises a first region, a well region between adjacent second grooves of the first region in the second cell further comprises a first part well region and a second part well region, the first part well region is close to the third groove, the second part well region is far away from the third groove, the first source region is located on the surface of the second part well region, and no source region exists on the surface of the first part well region.

The invention provides a process method for integrating a plurality of application voltage metal-oxide-semiconductor field effect transistor (MOSFET) devices. The method defines first, second and third voltage device regions on a semiconductor substrate. And when well regions required by the first and second voltage devices are formed, the first and second conduction type devices in the third voltage device region respectively borrow the corresponding well regions of the first or second voltage device. And opening a third voltage device region by using a newly added third application voltage photoetching mask, carrying out one-step threshold voltage regulation ion implantation, and simultaneously regulating threshold voltages of the two conduction type devices. And then forming a third gate dielectric layer and a gate structure. According to the invention, a high-performance medium-voltage device can be integrated with low cost on the basis of the existing double-gate oxide process only by adding a photomask and through ingenious well region borrowing and a single injection step.

The invention relates to a semiconductor chip with double-sided grooves and a manufacturing method thereof. Belongs to the technical field of power semiconductor devices. The problems that an existing single-groove chip is low in production efficiency, high in cost and limited in forward and reverse blocking voltage boosting are mainly solved. The device is mainly characterized in that the trenches are terminal double-sided trenches and are respectively and symmetrically arranged at P-N junction terminals of the N-type substrate, the anode P layer and the cathode P layer, and the inner surfaces of the trenches are provided with protective layers; and cathode P short-circuit points and cathode P + short-circuit points embedded in the cathode P short-circuit points are uniformly arranged in the cathode N + region, so that a low-resistance conductive current channel is formed. According to the invention, the design of a P-type punch-through ring structure is canceled, and the low-concentration P-type doping and high-concentration P + design is adopted, so that the short-circuit punch-through resistance can be reduced, the through-current capability and the blocking voltage of the chip can be improved, and the method is mainly used for manufacturing medium-voltage and high-voltage power semiconductor device chips.