Controlled silicon chip structure of mesa technology and implementation method

Abstract

The invention relates to a controlled silicon chip structure of a mesa technology. The structure comprises an N+ type cathode region, a front surface P-type short base region, a glass passivation film, front surface grooves, a SiO2 protective film, a silicon single crystal chip, a gate pole aluminum electrode and a cathode aluminum electrode, wherein the front side of the silicon single crystal chip is provided with the front P-type short base region; the back side of the silicon single crystal chip is provided with a P-type region; the surface of the front surface P-type short base region isprovided with the SiO2 protective film, the gate pole aluminum electrode and the cathode aluminum electrode; the front grooves are arranged on the front surface P-type short base region and the silicon single crystal chip, and are positioned at two sides of the gate pole aluminum electrode and the cathode aluminum electrode; and the N+ type cathode region is arranged between the cathode aluminum electrode and the front P-type short base region. The structure is characterized in that the bottom part of a dual-pass insulation diffusion region is provided with a back side stress balance groove. The structure provided by the invention has the advantages of mature structure and technology, simple manufacturing process, good breakdown voltage property of the manufactured chip, high percent of pass, and high reliability of products.

Description

technical field [0001] The invention relates to a structure of a thyristor chip of the mesa process, and also relates to an implementation method of the thyristor chip of the mesa process, which belongs to the technical field of power semiconductor device manufacturing. Background technique [0002] In the manufacture of power thyristor chips in medium and high voltage power semiconductor devices, mesa process manufacturing technology is still widely used, such as Figure 1-4 As shown, a layer of 30-50um thick passivation glass film is grown in the groove on the front of the silicon wafer, because the expansion coefficient of the glass film is much larger than that of silicon (generally the expansion coefficient of passivation glass is 4.4±0.4×10 -6 / °C, while the expansion coefficient of silicon is 2.6×10 -6 / °C), after the glass sintering is completed, the glass film in the front groove produces a large shrinkage stress, which pulls the silicon wafer to bend upwards. Due...

AI Technical Summary

Problems solved by technology

[0002] In the manufacture of power thyristor chips in medium and high voltage power semiconductor devices, mesa process manufacturing technology is still widely used, such as Figure 1-4 As shown, a passivation glass film with a thickness of 30-50um is grown in the groove on the front of the silicon wafer, because the expansion coefficient of the glass film is much larger than that of silicon (generally, the expansion coefficient of passivation glass is 4.4±0.4×10 -6 / °C, while the expansion coefficient of silicon is 2.6×10 -6 / °C), after the glass sintering is completed, the glass film in the front groove produces a large shrinkage stress, which pulls the silicon wafer to bend upwards. Due to the bending of the silicon wafer, the central area of ​​the silicon wafer and the photolithography mask cannot Cracks are generated due to close contact, resulting in waste products, often falling off, and a high rate of silicon wafer breakage. This method is only suitable for the process of Φ2-inch to Φ4-inch silicon wafers, and it is difficult to apply the above technology to Φ5-inch. ~Φ4 inch silicon wafer process

Images