Method for etching semiconductor structure and method for forming metal interconnection layer

Abstract

The invention provides a method for etching a semiconductor structure and a method for forming a metal interconnection layer. The method for etching the semiconductor structure comprises the steps of:providing a semiconductor substrate, wherein the substrate is provided with a patterned photoresist layer; taking the photoresist layer as a mask to perform plasma etching on the substrate, wherein aplasma etching process at least adopts three fluorocarbon compounds as etching gas; and removing the photoresist layer to form a semiconductor structure. The adoption of the method for etching the semiconductor structure can effectively improve the roughness of line edges of grooves formed by etching. The adoption of the method for forming the metal interconnection layer can effectively improve the roughness of the line edges of the grooves formed by etching, form the metal interconnection layer with straight line edges, and further improve the breakdown voltage characteristics of semiconductor devices.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an etching method for a semiconductor structure and a method for forming a metal interconnection layer. Background technique [0002] With the increasing demand for high integration and high performance of ultra-large-scale integrated circuits, semiconductor technology is developing towards technology nodes with 65nm or even smaller feature sizes, and the wavelength of light sources used for pattern exposure is also getting shorter and shorter. For example, using a 193nm wavelength The ArF laser is used as the light source to expose the key layer pattern of the integrated circuit with a line width below 65nm. Correspondingly, the photoresist material sensitive to the ArF laser (referred to as ArF photoresist) is also widely used in the photolithography process. [0003] The Chinese patent application with publication number CN101131918A provides a method for m...

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Problems solved by technology

[0004] However, since most ArF photoresists do not contain acidic alcohol groups, such photoresists have low affinity to alkaline developing solutions. Glue is more likely to produce the problem of Line Edge Roughness (LER), that is to say, the line edge of the photoresist pattern after exposure and development is jagged and uneven. Therefore, in the etching process, the photolithography The glue cannot effectively protect the underlying structure, and accordingly the edge of the groove formed by etching is also very rough

In addition, as the feature size of semiconductor devices becomes smaller and smaller, the thickness of ArF photoresist is also smaller and smaller. During the etching process, the thinner photoresist layer is over-etched, which is not enough to protect the underlying trench. edge, which will also roughen the edge of the trench line formed by etching

figure 2 It is a top view of the metal interconnect layer in a semiconductor device, such as figure 2 As shown, the grooves for the inlaid metal interconnection layer are etched with the rough-edged ArF photoresist pattern (not shown) as a mask. The light-colored lines in the figure are the line edges of the grooves. It can be seen that the grooves The edge of the line is uneven and rough. This is because the edge of the ArF photoresist layer is rough or thin during the etching process, which causes the edge of the groove under the photoresist layer to be over-etched, which will cause The line width of the metal wiring after forming the metal interconnection layer is uneven, which will seriously affect the breakdown voltage of the semiconductor device

[0005] Similarly, in other semiconductor manufacturing processes that use ArF light sources for lithography, such as the formation of gates and ohmic contacts, etch formation due to rough line edges of ArF photoresists or thin photoresist layers will also occur. The roughness of the line edge of the pattern, which has a bad influence on the reliability of the semiconductor device

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