Contact barrier layer deposition process

a technology of contact barrier layer and deposition process, which is applied in the direction of basic electric elements, semiconductor/solid-state device manufacturing, electrical equipment, etc., can solve the problems of affecting the reliability of the resulting ics, uniform tin layer being deposited across the si substrate surface,

a technology of contact barrier layer and deposition process, which is applied in the direction of basic electric elements, semiconductor/solid-state device manufacturing, electrical equipment, etc., can solve the problems of affecting the reliability of the resulting ics, uniform tin layer being deposited across the si substrate surface,

US20080132060A1Inactive Publication Date: 2008-06-05MACRONIX INT CO LTD
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  • Contact barrier layer deposition process
  • Contact barrier layer deposition process
  • Contact barrier layer deposition process

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BRIEF DESCRIPTION OF THE DRAWINGS

[0014]For a more complete understanding of the principles disclosure herein, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0015]FIG. 1 is a cross-sectional illustration of the various sub-layers of material that form a barrier layer over a semiconductor substrate, in accordance with one embodiment.

[0016]FIG. 2 is a top level illustration of a system for depositing a β€œmixed type” contact barrier layer onto a semiconductor substrate, in accordance with one embodiment.

[0017]FIG. 3A is a flowchart of a method to form a new contact barrier layer onto a semiconductor substrate, in accordance with one embodiment.

[0018]FIG. 3B is a flowchart detailing the operation of the ionized metal plasma (IMP) physical vapor deposition chamber to form a layer of Ti on a semiconductor substrate, in accordance with one embodiment.

[0019]FIG. 3C is a flowchart detailing the op...

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Abstract

A method for depositing a barrier layer onto a substrate is disclosed. A layer of titanium (Ti) is deposited onto the substrate using an ionized metal plasma physical vapor deposition process, wherein the layer of Ti has a thickness of between about 10 angstroms (β„«) and about 1000 β„«. A first layer of titanium nitride (TiN) is deposited onto the layer of Ti using a metal organic chemical vapor deposition process, wherein the first layer of TiN has a thickness of between about 1 β„« and about 100 β„«. A second layer of TiN is deposited onto the first layer of TiN using a thermal chemical vapor deposition process, wherein the second layer of TiN has a thickness of between about 10 β„« and about 750 β„«.

Description

BACKGROUND[0001]I. Field of the Invention[0002]The embodiments disclosed in this application generally relate to processes for depositing a contact barrier layer on an integrated circuit (IC) substrate.[0003]2. Background of the Invention[0004]In the formation of integrated circuit structures, an insulating layer is formed over active devices, or over a patterned underlying metal interconnect layer, and vertical openings are then formed through this insulating layer to provide electrical communication from the upper surface of the insulating layer to the underlying active device or electrical interconnect. Such openings are then filled with an electrically conductive material to provide electrical connection between the underlying elements and conductive materials, such as a metal interconnect, subsequently formed on the surface of the insulating material. In the fabrication of both horizontal and vertical interconnects, barrier layers are typically deposited over the patterned surf...

Claims

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Application Information

Patent Timeline
05 Jun 2008
Publication
US20080132060A1
IPC
H01L21/44
CPC
H01L21/2855; H01L21/76841; H01L21/28556
Inventors
LUOH, TUUNG; SU, CHIN-TA