70results about How to "Lower interface state" patented technology

The invention relates to the field of solar cell production method, especially to a method for realizing a laminated passivation film on the back surface of a solar cell. A film is deposited on the backlight surface of a processed solar cell silicon chip according to chemical vapor deposition technology, the mixed gas of SiH4 and N2O is adopted as the gas at the beginning of the deposition, NH3 is gradually added in the process of deposition so that the component of the film is changed from silicon dioxide on the surface of the silicon chip to nitrogen oxide of silicon in the outward direction and then to silicon nitride in the outward direction, and the thickness of the film ranges from 50nm to 300nm. The method has the characteristics of fast deposition speed, high output, being capable of achieving the deposition of a plurality of films at a time, and high tightness of the deposited film. High temperature process is not needed in the technology, the heat budget required is less, and high temperature influence resulted from thermal oxidization is avoided, in addition, such a graded laminated film can effectively reduce interface state caused by the combination of different films, improve thermal stability compared with silicon nitride only, and lessen film stress.

The invention discloses a method for realizing an enhanced HEMT (High Electron Mobility Transistor) by virtue of p-type passivation. The method comprises the following steps: providing a heterostructure which mainly comprises a first semiconductor and a second semiconductor, wherein the second semiconductor is distributed on the first semiconductor and is provided with a band gap wider than the first semiconductor, and two-dimensional electron gas is formed in the heterostructure; forming a p-type doped third semiconductor on the second semiconductor, performing passivation treatment on a residual region, except for an under-gate region, of the third semiconductor, so that the p-type doped region only exists at the under-gate region, and the under-gate region is distributed under a gate electrode of an HEMT device; manufacturing a source electrode, a drain electrode and a gate electrode connected with the heterostructure, electrically connecting the source electrode and the drain electrode through the two-dimensional electron gas, and enabling the gate electrode to be distributed between the source electrode and the drain electrode. The invention further discloses the enhanced HEMT. The method has the advantages of simple process, high repeatability, stable and favorable device performance, low cost, easiness for large-scale production and the like.

A semiconductor structure and a method of forming the same are disclosed. The method of forming the semiconductor structure comprises the steps of providing a semiconductor substrate comprising an NFET region and a PFET region, forming with a first fin portion and a second fin portion, the semiconductor substrate being provided with an isolation layer thereon, forming a dielectric layer on the isolation layer, the dielectric layer being provided internally with a first groove and a second groove, the first groove exposing the first pin portion partially and the isolation layer at the two sides of the first fin portion partially, and the second groove exposing partially the second fin portion and partially the isolation layer at the two sides of the second fin portion; forming a first interface layer on the surface of the first fin portion at the bottom of the first groove, and forming a second interface layer on the surface of the second fin portion at the bottom of the second groove; carrying out defect repair ion doping for the first interface layer; and after the defect repair ion implantation for the first interface layer, forming a first gate structure in the first groove, and forming a second gate structure in the second groove. The method can improve the performance of the formed substrate structure.

The invention discloses a method for improving the interface state of the back surface of a PERC battery and a battery prepared by the same and belongs to the solar cell technical field. The method includes the following steps that: 1) texturing, diffusion, etching and annealing process at an early stage is performed on a silicon wafer; and 2) plasmas are adopted to clean impurities on the back surface of the silicon wafer by means of a tubular plasma enhanced chemical vapor device, and an Al2O3 layer and a SiNx layer are successively deposited. According to the method of the present invention, the Al2O3 layer and the SiNx layer are sequentially deposited on the back surface of the PERC battery, and therefore, the interface state of the back surface of the battery can be reduced, a passivation effect can be improved, an EL problem caused by impurity adsorption during the back surface preparation process of the battery can be solved, the EL yield of battery sheets can be improved, and ahighly efficient high-yield PERC battery can be prepared.

The invention discloses an interface-optimized germanium-based semiconductor device and a method for manufacturing the same, wherein an optimized interface layer with high thermostability is formed on a germanium-based substrate, and then a semiconductor device is formed on the optimized interface layer. As the optimized interface layer has higher thermostability and has good compatibility with high k-gate media, the interface thermostability of the device is effectively enhanced; and in addition, the interface charge and the interface state are lowered.

The invention discloses an enhancement mode device based on fluoride ion injection and a manufacturing method of the enhancement mode device based on fluoride ion implantation. The enhancement mode device based on fluoride ion injection comprises a substrate, an epitaxy multilayered structure formed on the substrate, a grid electrode, a source electrode and a drain electrode, wherein the grid electrode, the source electrode and the drain electrode are arranged on the epitaxy multilayered structure, and fluoride ions are injected in a heterogeneous structure layer below the grid electrode in a tunnel injection mode and are used for using up two-dimensional electron gas in the heterogeneous structure layer. As the fluoride ions are injected in the heterogeneous structure layer below the grid electrode in the tunnel injection mode and use up the two-dimensional electron gas in the heterogeneous structure layer below the grid electrode, the enhancement mode gallium nitride device is achieved. Meanwhile, unstable fluoride ions are removed through high temperature annealing, crystal lattices recover from damage caused when the fluoride ions are injected, and a crystalline state medium layer is utilized for protecting surfaces of nitride materials produced during high temperature annealing.

The invention discloses a high electron mobility transistor and a manufacturing method thereof. A recessed gate is formed through manufacturing a secondary epitaxial barrier layer in a gate area on afirst thin AlGaN barrier layer, epitaxially growing a second AlGaN barrier layer and a GaN cap layer on the first thin AlGaN barrier layer in sequence and removing the barrier layer. Therefore, any dry and wet etching process is not needed when the recessed gate is manufactured, the damage of etching to the surfaces of the AlGaN barrier layers is avoided and the interface state is reduced to ensure excellent performance of the transistor; and in addition, the recessed gate is achieved through secondary epitaxy of AlGaN, so that the transistor has double AlGaN barrier layers, sufficient electrons in a channel are ensured and the transistor has relatively high breakover current.

Methods for fabricating a layer of oxide on a silicon carbide layer are provided by forming the oxide layer by at least one of oxidizing the silicon carbide layer in an N2O environment or annealing an oxide layer on the silicon carbide layer in an N2O environment. Preferably, a predetermined temperature profile and a predetermined flow rate profile of N2O are providing during the oxidation or the anneal. The predetermined temperature profile and/or predetermined flow rate profile may be constant or variable and may include ramps to steady state conditions. The predetermined temperature profile and/or the predetermined flow rate profile are selected so as to reduce interface states of the oxide/silicon carbide interface with energies near the conduction band of SiC.

The invention discloses a manufacture method of a low-interface-state device. The manufacture method comprises the following steps: carrying out remote plasma surface treatment on group III nitride layers on a pair of substrates; transferring the treated substrates to a deposition chamber via an anaerobic transmission system; and depositing on the treated substrates in the deposition chamber. The deposition can be low-pressure chemical vapor deposition (LPCVD). The interface state between a surface medium and a group III nitride material can be obviously reduced by integrating low-damage remote plasma surface treatment and the LPCVD technique.

The invention discloses a vertical GaN Schottky diode based on an in-situ growth MIS structure, which comprises a substrate and is characterized in that the bottom of the substrate is provided with a cathode, the top of the substrate is sequentially provided with an n + layer and a drift region from bottom to top, the top of the drift region is provided with an in-situ growth dielectric layer, and the top of the dielectric layer is provided with an anode. The invention also provides a preparation method of the diode, and the method comprises the following steps: S1, providing a substrate, carrying out the pretreatment and heat treatment of the substrate, and depositing an n+ layer on the substrate; S2, depositing a drift region with a thickness of 1-10 [mu]m on the n + layer; S3, directly growing a dielectric layer on the GaN drift region in situ; S4, depositing cathode metal at the bottom of the substrate; and S5, manufacturing a mask on the dielectric layer, and depositing anode metal on the dielectric layer to obtain the Schottky diode. The diode provided by the invention is high in interface quality and beneficial to long-term reliability.

The invention discloses a preparation method of a trench PMOS (positive-channel metal oxide semiconductor) enabling the side wall of a trench to be the (110) surface, which comprises the following steps: enabling the side wall surface of the trench after etching to be the (110) crystal surface when defining a trench pattern on a substrate through the photoetching process; injecting nitrogen ions into the inner wall of the trench after forming the trench by etching; and then growing a gate oxide on the inner wall of the trench. By adopting the method, the threshold voltage of the PMOS device can be effectively reduced to achieve the application requirement.

The invention discloses a method for preventing transverse diffusion of ohmic contact aluminum in a GaN-based device. Ohmic contact aluminum is deposited in pores of a heat-resisting silicon nitride medium, transverse diffusion of ohmic contact aluminum is blocked by the heat-resisting silicon nitride medium, surface protection for ohmic alloy is further realized, and interface pollution and interface state are reduced. The method comprises: the heat-resisting silicon nitride medium grows on the surface of an epitaxial material; pores are formed in the high-temperature silicon nitride medium covering the area of an ohmic contact metal pattern; ohmic contact metal is evaporated in the formed pores of the silicon nitride medium to form metal stacking, wherein the upper surface of the silicon nitride medium is not lower than the upper surface of a stacked metal aluminum layer in the area of the formed pores. The method solves the problem of aluminum transverse diffusion in ohmic contact preparation of the GaN-based device, avoids the risk that the device performance is degraded due to a polluted material surface in a high-temperature alloy technology, further realizes surface protection of ohmic alloy, and reduces interface pollution and interface state.

The present invention discloses a manufacturing method of an Ohmic contact structure of a nitride semiconductor device. The method comprises the steps of: forming a metal stacked structure including an Al layer on a GaN substrate, performing low-temperature oxidation in an oxygen atmosphere to form an aluminum oxide barrier layer at the side wall of the Al layer, and forming Ohmic contact of the metal stacked structure and the GaN substrate through high-temperature alloy. The low-temperature oxidation processing is performed prior to Ohmic contact alloy to allow the outer side of the Ohmic metal to be oxidized to aluminum oxide so as to reduce the interface pollution or improve an interface state; and moreover, the method increases low-temperature oxidation in a traditional GaN device Ohmic metal manufacturing process, is simple in process with no need for introducing other substances and other materials, and is high in practicability and good in effect.

The invention relates to the field of semiconductor memories, and discloses a TN (tunnel nitrate)-SONOS (silicon oxide nitrate oxide silicon) memory with a composite nitrogen-based dielectric tunneling layer. The TN-SONOS memory comprises a semiconductor substrate, a grid electrode and a dielectric laminate; the semiconductor substrate comprises a channel, a source terminal and a drain terminal, and the source terminal and the drain terminal are adjacent to the channel; the dielectric laminate is arranged between the grid electrode and the surface of the channel and comprises a tunneling layer, a charge trapping layer and a stopping layer, the tunneling layer is in contact with the surface of the channel, the charge trapping layer is laminated on the upper side of the tunneling layer, and the stopping layer is laminated on the upper side of the charge trapping layer and is in contact with the grid electrode; and the tunneling layer is the composite dielectric tunneling layer and comprises a first layer consisting of silicon oxynitride SiON(x), a second layer consisting of Si3N4 and a third layer consisting of silicon oxynitride, SiON(y), the first layer is in contact with the surface of the channel, the second layer is adjacent to the first layer, and the third layer is adjacent to the second layer. By the TN-SONOS memory, the performance of a SONOS nonvolatile memory is improved, and the TN-SONOS memory can be applied to extremely small memory devices with high quality.

The invention discloses a silicon-germanium heterojunction solar cell. The structure of the silicon-germanium heterojunction solar cell sequentially comprises a silver electrode, an aluminum-doped zinc oxide (AZO) conductive layer, n-type monocrystalline silicon, an i-type SiGe alloy buffer layer film, a p-type Ge film and a gold electrode from top to bottom. The silicon-germanium heterojunction solar cell has a broad spectrum response value of 300-1800nm. According to the cell disclosed by the invention, a SiGe alloy buffer layer is deposited between silicon and germanium, thereby being capable of effectively reducing the interface state, reducing interface recombination, and increasing open-circuit voltage of the cell. In addition, a band gap of the buffer layer changes gradually, so that sunlight can be absorbed better, and short-circuit current of the cell is increased. The invention further discloses a preparation method of the silicon-germanium heterojunction solar cell. The preparation method is safe in raw material, capable of directly applying existing equipment and relatively low in cost.

A semiconductor device according to the embodiments includes a SiC layer having a first plane, an insulating layer, and a region between the first plane and the insulating layer, the region including at least one element in the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium), a full width at half maximum of a concentration peak of the element being equal to or less than 1 nm, and when a first area density being an area density of Si (silicon) and C (carbon) including a bond which does not bond with any of Si and C in the SiC layer at the first plane and a second area density being an area density of the element, the second area density being equal to or less than 1 2 of the first area density.