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Method for manufacturing p-type GaN low-resistance-value ohmic contact layer

A technology of ohmic contact layer and low resistance value, which is applied in the direction of electrical components, circuits, semiconductor devices, etc., can solve the problem of low resistivity, reduce the working voltage, increase the probability of tunneling through the contact barrier region between metal and semiconductor, Ease of promoting the effect of the application

Active Publication Date: 2015-02-25
XIANGNENG HUALEI OPTOELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In addition, the higher the doping concentration, the higher the hole concentration generated, and the lower the resistivity

Method used

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  • Method for manufacturing p-type GaN low-resistance-value ohmic contact layer
  • Method for manufacturing p-type GaN low-resistance-value ohmic contact layer
  • Method for manufacturing p-type GaN low-resistance-value ohmic contact layer

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Embodiment 1

[0024] Such as figure 1 As shown, the flow chart of the preparation method of the p-type GaN low-resistance ohmic contact layer provided by the present invention sequentially includes processing the substrate 101, growing a buffer layer 102 on the substrate, growing a u-type GaN layer 103 on the buffer layer, growing an n-type GaN layer 104 on the u-type GaN layer, growing an MQW active layer 105 on the n-type GaN layer, growing an AlGaN layer 106 on the MQW active layer, growing a first p-type GaN layer 107 on the AlGaN layer, and A second p-type GaN layer 108 is grown on the first p-type GaN layer, the Mg concentration in the second p-type GaN layer is greater than the Mg concentration in the first p-type GaN layer, the second p-type GaN layer and the first p-type GaN layer The layers are grown under the same temperature condition and the same pressure condition, and the growth rate of the second p-type GaN layer is 1 / 5-1 / 3 of the growth rate of the first p-type GaN layer. ...

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Abstract

The invention discloses a method for manufacturing a p-type GaN low-resistance-value ohmic contact layer. The method is characterized by sequentially comprising the steps that a substrate is processed, a buffer layer is grown on the substrate, a u-type GaN layer is grown on the buffer layer, an n-type GaN layer is grown on the u-type GaN layer, an MQW active layer is grown on the n-type GaN layer, an AlGaN layer is grown on the MQW active layer, a first p-type GaN layer is grown on the AlGaN layer, and a second p-type GaN layer is grown on the first p-type GaN layer. Compared with the prior art, due to the fact that the second p-type GaN layer has high Mg concentration doping, the hole concentration of the contact layer is high, the contact resistivity of the second p-type GaN layer and metal is reduced, a barrier region generated by the second p-type GaN layer and the metal becomes narrow, the probability that a carrier penetrates through a metal and semiconductor contact barrier region through tunneling is increased, the work voltage of a high-power LED chip is reduced, and therefore the light emitting efficiency of the high-power LED chip is improved.

Description

technical field [0001] The present application relates to the technical field of semiconductor lighting, in particular to a preparation method of a p-type GaN low-resistance ohmic contact layer. Background technique [0002] Light-emitting diode (LED), as a new type of high-efficiency, environmentally friendly and green solid-state lighting source, has the advantages of small size, light weight, long life, high reliability and low power consumption, making it widely used. In particular, with the rapid development of the LED industry, the proportion of LED applications in the lighting field is getting higher and higher. With the wide application of high-power LED chips in the field of lighting, the requirements for the luminous efficiency of high-power LED chips are increasing day by day. To achieve high-power LED chip luminous efficiency, on the one hand, the brightness of high-power chips must be improved, and on the other hand, the high-power chips must be reduced. Operat...

Claims

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Application Information

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IPC IPC(8): H01L33/00H01L33/40
CPCH01L33/0075H01L33/14
Inventor 刘为刚
Owner XIANGNENG HUALEI OPTOELECTRONICS
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