Manufacturing method of gate-all-around transistor

Abstract

The invention provides a method for preparing a gate-all-around transistor, the method comprising: 1) providing an SOI substrate with a groove formed in its insulating layer; 2) forming a semiconductor nanowire structure suspended and straddling the groove; 3) Rounding and thinning the semiconductor nanowire structure; 4) forming an implantation barrier layer on the surface of the channel region, the implantation barrier layer reveals the preparation area of ​​the source region and the drain region; 5) performing an ion implantation process to form the source region and drain region; 6) forming a fully-enclosed gate dielectric layer and a gate electrode layer on the surface of the semiconductor nanowire, and patterning to form a gate structure; 7) forming a source electrode and a drain electrode. The gate-all-round transistor of the present invention is prepared by a gate-last process, which can effectively increase the selection range of gate materials, thereby realizing different device performance requirements. The invention does not need isotropic wet etching when preparing semiconductor nanowires, and can effectively avoid the generation of concave cavities.

Description

technical field [0001] The invention belongs to the field of design and manufacture of semiconductor integrated circuits, in particular to a preparation method of a gate-around transistor. Background technique [0002] As microelectronic devices continue to shrink, it is expected that the existing FinFET technology will face a large technical bottleneck at the 5nm and 3nm nodes, and the device performance will no longer be greatly improved as the device size continues to decrease. This requires us to adopt new device technologies, such as new device materials (such as strained silicon, silicon germanium, germanium, III-V semiconductors, etc.), and new device structures (such as nanowire gate-around transistors, etc.). [0003] The nanowire gate-all-around transistor can confine the conductive channel to the center of the nanowire, rather than the interface between the nanowire and the gate oxide layer, which greatly reduces the scattering of carriers. It is expected that the...

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Problems solved by technology

[0015] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for preparing a gate-all-round transistor, which is used to solve the problem of low process stability in the preparation of a gate-all-around transistor in the prior art

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