Three-dimensional stacked gate-all-around transistor and preparation method thereof

Abstract

The invention provides a three-dimensional stacked gate-all-around transistor and a preparation method thereof, and the method comprises the steps: 1), providing an SOI substrate, and forming a groovein the insulating layer of the SOI substrate; 2) forming a semiconductor nanowire structure which is suspended, stretches across the groove and is stacked upwards; 3) rounding and thinning the semiconductor nanowire structure; 4) forming a fully-enclosed gate dielectric layer and a gate electrode layer on the surface of the semiconductor nanowire; 5) taking the gate electrode layer as a mask, andperforming ion implantation to form a source region and a drain region; 6) removing the gate dielectric layer outside the gate electrode layer; and 7) forming a source electrode and a drain electrodein the source region and the drain region. According to the invention, the gate electrode layer is used as a mask to carry out self-aligned injection of the source region and the drain region, so that the process stability and the injection precision can be effectively improved. When the semiconductor nanowire is prepared, isotropic wet etching is not needed, and the generation of a concave cavity can be effectively avoided. The integration level of the device can be effectively improved.

Description

technical field [0001] The invention belongs to the field of design and manufacture of semiconductor integrated circuits, in particular to a three-dimensional stacked gate-around transistor and a preparation method thereof. Background technique [0002] As microelectronic devices continue to shrink, it is expected that the existing FinFET technology will face a large technical bottleneck at the 5nm and 3nm nodes, and the device performance will no longer be greatly improved as the device size continues to decrease. This requires us to adopt new device technologies, such as new device materials (such as strained silicon, silicon germanium, germanium, III-V semiconductors, etc.), and new device structures (such as nanowire gate-around transistors, etc.). [0003] The nanowire gate-all-around transistor can confine the conductive channel to the center of the nanowire, rather than the interface between the nanowire and the gate oxide layer, which greatly reduces the scattering o...

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Problems solved by technology

[0015] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a three-dimensional stacked gate-all-round transistor and its preparation method, which are used to solve the problems of low process stability and low integration in the preparation of gate-all-round transistors in the prior art. low problem

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