56results about How to "Increase the current switch ratio" patented technology

The invention discloses a nano-wire field effect transistor comprising a gate electrode, a source region, a drain region, a central region and a gate dielectric layer. The central region is in the core-shell structures which are coaxial; the gate dielectric layer fully surrounds the central region; the gate electrode fully surrounds the gate dielectric layer; the source region and the drain region are respectively arranged on two sides of the central region; the core structure of the central region is made from insulating material, and the shell structure of the central region is made from semiconductor material; the doping type and the doping concentration of the semiconductor material of the shell structure of the central region are adjustable; the lengths of both the core structure and the shell structure and the radii of both the core structure and the shell structure are adjustable; and the materials of the gate dielectric layer, the gate electrode, the source region and the drain region are adjustable. Due to the adoption of the insulating core structure, the off-current of the traditional nano-wire transistor can be reduced effectively, and the current on-off ratio of the devices can be increased. The threshold voltage shifting and the drain induced barrier lowering of the nano-wire field effect transistor are less affected by the short channel effect, and the size reducing performance of the nano-wire field effect transistor is more excellent.

The invention provides an inorganic metal oxide semiconductor film of a perovskite structure and a metallic oxide thin film transistor. The inorganic metal oxide semiconductor film of the perovskite structure is used as an active layer. The inorganic metal oxide semiconductor film of the perovskite structure is expressed as the chemical expression: MxA1-xBo3, wherein 0.01<=x<=0.5, A is at least one chemical element of Ca, Sr and Ba, B is a chemical element of Ti and Sn, and M is at least one chemical element of Sc, Y, rare earth elements, Al and In. The inorganic metal oxide semiconductor film of the perovskite structure is composed of crystal particles of the perovskite structure, and sizes of the crystal particles vary from 2mm to 900mm. The thickness of the inorganic metal oxide semiconductor film of the perovskite structure varies from 10nm to 500nm. When the inorganic metal oxide semiconductor film of the perovskite structure is used as the active layer, electronic mobility is high, and the metallic oxide thin film transistor prepared by using the inorganic metal oxide semiconductor film of the perovskite structure is good in light stability, low in sub-threshold swing amplitude, simple in preparation technology and low in cost.

The invention discloses an ultra-low-power organic resistance changing memory device and a manufacturing method of the ultra-low-power organic resistance changing memory device, belonging to the technical field of organic electronics and CMOS-mixed integrated circuit. The device is manufactured on a substrate, a device unit is an MIM capacity structure, a bottom layer of the MIM structure is an inert electrode such as metal or non-metal conductive thin-film, a top layer of the MIM structure is an active electrode such as metal Al, a middle function layer of the MIM sturcture is a poly-p-xylylene polymer film growing after multi-deposition. According to the invention, the device adopts the poly-p-xylylene polymer film growing after multi-deposition as the function layer, programming current of a memory is less than 0.5 muA, and erase current of the memory is reduced to about 10 nA or lower, therefore, the ultra-low-power operations of the organic resistance changing memory are implemented.

The invention provides an asymmetric van der Waals heterojunction device, comprising graphene nanosheets, hexagonal boron nitride nanosheets, molybdenum disulfide nanosheets and molybdenum telluride nanosheets sequentially arranged from bottom to top; The graphene nano sheet and the hexagonal boron nitride nano sheet, the molybdenum disulfide nano sheet and the molybdenum telluride nano sheet havean overlapping region; A surface area of that molybdenum disulfide nanosheet is lar than that of the molybdenum telluride nanosheet, and parts of the molybdenum disulfide nanosheet do not overlap with the molybdenum telluride nanosheet. The invention also provides the preparation and application of the asymmetric van der Waals heterojunction device. The asymmetric van der Waals heterojunction device of the invention can realize the organic unity of ultra high performance and multiple functions. When operating as a transistor, the device exhibits ultra-high current switching ratio, ultra-smallsubthreshold swing and obvious negative transconductance behavior. When operating as a rectifier, the device exhibits an ultra-high current rectification ratio. When operating as memory, the device exhibits an ultra-high erase/write current ratio and current rectification ratio.

The invention discloses an asymmetric reconfigurable field effect transistor. The transistor includes a trench; a drain electrode arranged at one end of the trench; a source electrode which is arranged at the other end of the trench and extends into the trench; gate oxide which is arranged at the outer side of the channel; a control grid electrode and a polar grid electrode which are respectivelyarranged at the source electrode end and the drain electrode end and outside the grid electrode oxide; side walls which are respectively arranged outside the two ends of the trench and used for electrically isolating the control grid electrode, the polar grid electrode, the source electrode and the drain electrode; and the grid isolation part which is arranged outside the grid electrode oxide andused for isolating the control grid electrode from the polar grid electrode. The contact area between the source end extending into the trench and a nanowire trench is larger, the tunneling area of carriers is increased, and the starting current is increased. In a switching-off state, a drain electrode structure and a common RFET drain electrode structure have the same non-overlapping area, and aleakage current is basically kept unchanged, so that the current switch ratio is improved, and the operation delay time of a logic gate current is shortened under the condition that the static power consumption is not changed.

The invention belongs to the technical field of display devices, and discloses a praseodymium indium zinc oxide thin film transistor and a preparation method thereof. The thin film transistor is composed of a substrate, a metal gate, a gate insulating layer, a Pr-IZO semiconductor active layer, an oxide insulator passivation layer and metal source drain electrodes. Pr element doping is introducedinto the IZO semiconductor, and a Pr-IZO active layer thin film is deposited by a room temperature sputtering process; and by combination of an ultra-thin Al<2>O<3> passivation layer, carrier transportation under an electric field is controlled, so that the high-mobility and high-current-switching-ratio oxide thin film transistor can be realized at room temperature.

The invention discloses a nano-sheet ring gate field effect transistor with an asymmetric gate oxygen structure. The nano-sheet ring gate field effect transistor comprises a vertically stacked nano-sheet channel, a double-layer gate oxide wrapping outside the channel, a source and a drain arranged at the two ends of the channel, a double-layer side wall and a substrate arranged at the bottom. Thenano-sheet ring gate field effect transistor is characterized in that the gate oxide is formed by stacking a low dielectric constant material and a high dielectric constant material and is divided into two parts near the drain and the source with half of the channel length as the boundary. The total physical thickness of gate oxygen in the two parts is the same, and the low dielectric constant gate oxide is thinner and the high dielectric constant gate oxide is thicker in the double-layer gate oxides near the drain so as to form the nano-sheet ring gate field effect transistor with the asymmetric gate oxygen structure. Compared with the prior symmetrical type technology, the drain end electric field is lower and the hot carrier effect of the device can be effectively inhibited; it has moreideal on-state and off-state current and higher current switching ratio;and the leakage potential is more stable, the leakage-induced barrier reduction effect is suppressed and the short channel characteristics are improved.

The present invention provides a Schottky barrier transistor and a preparation method thereof. The Schottky barrier transistor includes a substrate and a gate structure on the substrate. The Schottkybarrier transistor further includes: a channel region located at the surface of the substrate corresponding to the gate structure, wherein the channel region comprises a first metal silicide layer; and a source-drain region comprising a second metal silicide layer and a third metal silicide layer located at two sides of the channel region, wherein the second metal silicide layer is located in thesubstrate, the third metal silicide layer is located at the surface of the substrate corresponding to the second metal silicide layer, and the work function of the second metal silicide layer is smaller than the work function of the third metal silicide layer. The Schottky barrier transistor has a high mobility channel to improve the device on-state current and reduce the off-state current of thetransistor so as to improve the current switching ratio of the device.

An ambipolar inverter device suitable for use in an integrated circuit. An electron blocking layer and a hole blocking layer are respectively disposed at two sides of the ambipolar semiconductor layer, so that the operation of the inverter may be executed in a single device. In addition, the manufacturing method of the disclosure is simple, adopting only one patterning step, so as to effectively improve the performance of the ambipolar device.

The invention discloses a reconfigurable field effect transistor with a structure of asymmetric sidewalls and vertically stacked channels. The transistor comprises multiple vertically stacked channels, gate oxides wrapping the outer side of the channels, source and drain electrodes which are arranged on the two ends of the channels, a source sidewall arranged at the right side of the source electrode, a source sidewall arranged at the left side of the drain electrode, a control gate arranged at the right side of the source sidewall, a polar gate arranged at the left side of the drain sidewall,a gate isolation arranged between the control gate and the polar gate and a substrate arranged at the bottom. The transistor is characterized in that the source sidewall and the drain sidewall use different materials, and the length of the source sidewall is less than or equal to the length of the drain sidewall; and the channels are stacked at least twice along the direction perpendicular to thesubstrate. The higher current density can be obtained on the same area so that the effect of reducing the delay of the combinational logic and improving the current driving ability can be achieved.

The invention provides a transistor and a production method thereof. The production method includes the following steps: a semiconductor substrate is provided; a high K gate medium layer, a metal material layer and a sacrificial material layer are sequentially deposited on the semiconductor substrate; partial sacrificial material layer and partial metal material layer located right under the sacrificial material layer are removed, and a stacked structure comprising the sacrificial material layer and the metal material layer and used for defining the area where a transistor fate is located is formed on the semiconductor substrate; a side wall material layer is deposited on the semiconductor substrate provided with the stacked structure; and the stacked structure and the side wall material layer located above the high K gate medium layer are removed, the side wall material layer remained on two sides of the stacked structure forms side walls of the stacked structure, and the high K gate medium layer not covered by the stacked structure is removed. The high K gate medium layer in the formed transistor cannot cause current leakage so that current switching ratio, Gate Induced Drain Leakage (GIDL) performance and the like of the transistor are improved, and the transistor gate can generate little current leakage.

The invention relates to an oxide semiconductor device which includes an insulating substrate; a source electrode and a drain electrode are oppositely arranged on the insulating substrate; a nanosheet stack part is included and is arranged on the substrate to form a plurality of conducting channels; the nanosheet stack part comprises a plurality of metal oxide semiconductor nanosheets which are vertically stacked to form the nanosheet stack part, and the two ends of the metal oxide semiconductor nanosheets are embedded into the source electrode and the drain electrode respectively; and a surrounding type grid electrode is included and surrounds the periphery of the plurality of metal oxide semiconductor nanosheets in the nanometer stack part. The design of the novel structure gate-all-around OS-TFT (GAA OS-TFT) can significantly improve the sub-threshold characteristic, the current switch ratio and the short channel effect of the device; the working current of the device can be obviously improved by utilizing the design of combining the multiple layers of nanosheets and the supporting structure; the preparation process of the device is compatible with a mainstream CMOS process and is simple; and through the structure design of the surrounding type grid device, the channel carrier mobility can be remarkably improved, the electrical performance of the device is increased, and the reliability and the stability of the device can also be improved.

The invention provides an organic thin film transistor and a preparation method thereof, which belong to the technical fields of organic electronics and photo-electronics. The organic thin film transistor includes a substrate, a source-drain layer containing a source and a drain, an organic semiconductor layer, a gate insulating layer and a gate layer. One surface of the substrate is the source-drain layer. The surface of the source-drain layer away from the substrate is the organic semiconductor layer. The surface of the organic semiconductor layer away from the source-drain layer is the gateinsulating layer. The surface of the gate insulating layer away from the organic semiconductor layer is the gate layer. The source-drain layer is made of conductive ink. The preparation method of theorganic thin film transistor includes the following steps: coating one surface of a substrate with conductive ink; curing the conductive ink to form a first electrode layer; and exposing, developingand heat-treating the first electrode layer to obtain a source-drain layer. The organic thin film transistor prepared by the method needs neither a flat layer nor a photoresist layer, and can be patterned directly.

The invention belongs to the technical field of semiconductors, and discloses an ultraviolet photodiode and a preparation method thereof. The ultraviolet photodiode comprises the following structures:a substrate; a GaN layer which is arranged on the upper surface of the substrate; a Ti3C2 Schottky contact layer and a ohmic contact layer which are oppositely arranged on the two sides of the uppersurface of the GaN layer; and a metal contact layer which is arranged on the upper surface of the Ti3C2 Schottky contact layer. The ultraviolet photodiode has the advantages of excellent ultraviolet detection performance, high responsivity, high specific detection rate, high response speed and high current switch ratio; and the preparation method does not need a complex metal deposition or sputtering process, does not damage the surface of the semiconductor, and is simple in process.

The invention discloses an electric heating fabric with a pressure sensitive characteristic, a preparation method of the electric heating fabric, and an electric blanket and a bedding made of the fabric with the pressure sensitive characteristic. The electric heating fabric with the pressure sensitive characteristic comprises a fabric layer and an electric heating film, the electrothermal film is provided with a lower protection layer, a heating layer, an upper protection layer, an electrode attached to the heating layer and a lead-out wire. The heating layer is prepared from the following components: 95 to 98 weight percent of polyurethane resin, 2 to 5 weight percent of graphene and 0.01 to 0.5 weight percent of black phosphorus/metal oxide nano composite material. The polyurethane film is filled with the graphene filler which is slightly lower than the conductive percolation threshold range of the polyurethane film, and a small amount of black phosphorus/metal oxide nano composite material is added to enhance the pressure sensitive characteristic of the film. After the electric heating film of the electric heating fabric is connected with a power supply, when no external pressure exists, the resistance of the heating layer is large, and the heating layer does not emit heat; when the outside endows the electrothermal film with certain pressure, the electrothermal film begins to heat, and after the external force disappears, the heating layer restores to the original shape and stops heating.

The invention relates to a rhenium disulfide-based field effect transistor and a manufacturing method thereof, the rhenium disulfide-based field effect transistor comprises a substrate, the substrate comprises a silicon substrate and an oxide layer growing on the silicon substrate, a rhenium disulfide channel is etched on the oxide layer, the field effect transistor further comprises a drain-source electrode growing in the source-drain contact region, a gate oxide layer covering the rhenium disulfide channel and a metal lead located at the bottom of the silicon substrate, a gate electrode grows on the gate oxide layer, and the drain-source electrode comprises a Cr electrode and an Au electrode which are sequentially located on the oxide layer. The field effect transistor has a high switching current ratio, the short channel effect caused by device size reduction is effectively reduced, and meanwhile, the structure of the top gate and the back gate is also beneficial to regulation and control of source and drain currents.