52results about How to "Increase turn-on current" patented technology

A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.

The present invention relates to an array substrate and a manufacture method of the same, a liquid crystal display panel, and a display device, which are relative to a liquid crystal display field. Further, source electrodes and drain electrodes of the array substrate are arranged on different layers. In the manufacture method of the array substrate, the source electrodes and the drain electrodes are formed on different layers by two patterning processes. According to the technical scheme of the present invention, a length of a channel between the source electrodes and the drain electrodes can be decreased as much as possible, thereby increasing a start current Ion of a TFT.

The invention belongs to the technical field of semiconductor devices, and particularly relates to a U-shaped channel tunneling transistor with a laminated structure and a preparation method thereof. According to the invention, a highly doped silicon layer of which the doping type is opposite to that of a SiGe source area is formed under the SiGe source area of the tunneling transistor by an epitaxial growth method; and the forbidden bandwidth of the SiGe is narrower than that of silicon, so that the band bending degree between the source area and a channel region can be improved, then the length of tunneling can be reduced and the tunneling efficiency is improved. The U-shaped channel tunneling transistor with the laminated structure which is provided by the invention can substantially improve firing current and reduces subthreshold swing under the circumstance that shutdown current is not influenced.

The invention relates to a double-grid electric charge capturing memory based on a polycrystalline silicon nanowire field effect transistor and a manufacture method thereof. The double-grid electric charge capturing memory is provided with two polycrystalline silicon grid electrodes, and comprises a semiconductor substrate, a first dielectric buffer layer formed on the semiconductor substrate, a second dielectric buffer layer formed on the first dielectric buffer layer, a polycrystalline silicon bottom grid formed on the second dielectric buffer layer, two nanowire channels symmetrically distributed on the two sides of the polycrystalline silicon bottom grid, two electric charge capturing memory dielectric layers formed between the polycrystalline silicon bottom grid and the nanowire channels respectively, two top grid dielectric layers formed on the outer side of the two nanowire channels, a hard masking layer formed on the polycrystalline silicon bottom grid, the electric charge capturing memory dielectric layers, the nanowire channels and the top grid dielectric layers, a polycrystalline silicon top grid formed on the hard masking layer and the electric charge capturing memory dielectric layers and a source region and a drain region, spanning the two nanowire channels.

The invention discloses an asymmetrical reconfigurable field effect transistor. The transistor comprises a channel, a drain arranged at one end of the channel, a source extended to the inside of the channel at the other end of the channel, and a drain arranged at one end of the channel. The gate oxide on the outside, the control gate and the polarity gate respectively arranged on the source and drain terminals and outside the gate oxide, respectively arranged outside the two ends of the channel, are used for the control gate, the polarity gate The side wall electrically isolating the source and the drain, and the gate isolation arranged outside the gate oxide for isolating the control gate and the polarity gate. In the present invention, the contact area between the source end extending into the channel and the nanowire channel is larger, thereby increasing the tunneling area of ​​carriers and increasing the turn-on current. When it is turned off, the drain structure is the same as the non-overlapping area of ​​the general RFET drain structure, and the leakage current remains basically unchanged, so the current switching ratio is improved, and the logic gate current is shortened while keeping the static power consumption unchanged. operation delay time.

A metal oxide semiconductor field effect transistor and its manufacturing method, the metal oxide semiconductor field effect transistor is characterized by a trench in the semiconductor substrate, and the channel region is a doped semiconductor across the trench thin layer, and the gate is located in the trench and above the trench, and surrounds the channel region through the gate dielectric layer. The steps of another manufacturing method are as follows: first, a semiconductor substrate is provided, and then a trench is formed on it. Then fill up the trench with a sacrificial layer, form a doped semiconductor layer, and define it to form an element region. The element region crosses the sacrificial layer and exposes a part of the sacrificial layer. Then the sacrificial layer is removed to expose the lower surface of the element region above the trench, and then a gate dielectric layer is formed on the surface of the element region and the trench. Next, a conductor layer is formed on the gate dielectric layer and filled into the trench, and then the conductor layer is defined to form a gate located in and above the trench. Then, a source and a drain are formed on both sides of the gate.

An embodiment of the disclosed technology provides a driving device for a thin film transistor liquid crystal display (TFT-LCD) and a method for manufacturing the same. The driving device comprises at least one first TFT and at least one second TFT formed a base substrate, wherein load of the first TFT is larger than load of the second TFT, the first TFT is of a top-gate configuration, and the second TFT is of a bottom-gate configuration.

The invention discloses a method for manufacturing a metal oxide semiconductor field effect transistor and a device thereof. The manufacturing method comprises the following steps: providing a semiconductor substrate; forming an insulating layer on the surface of the semiconductor substrate; forming a groove on the insulating layer; forming light dope drain regions in the semiconductor substrate below the lateral wall of the groove respectively; forming grid flank walls on the lateral wall of the groove respectively; forming grid dielectric layers on the groove surfaces between the grid flank walls; forming grids in an accommodating space encircled by the grid flank walls and the grid dielectric layers; removing the insulating layer; and forming a source region and a drain region respectively in the semiconductor substrates on two sides of the grid flank walls. The manufacturing method breaks through the limitation of the minimum grid length which can be achieved by a photoetching device, and reduces the length of a channel formed between the source region and the drain region; and the device formed according to the method is helpful for enhancing the firing current and reducing the electric leakage caused by short-channel effect.

The invention discloses a novel asymmetric double-gate junctionless field effect transistor comprising a top gate, a bottom gate, a source region, a drain region, gate dielectric layers, a channel overlap region, and channel non-overlap regions. The top gate and the bottom gate are respectively disposed in an upper position and in a lower position of a channel, and are of an asymmetric structure. There is an overlap region between the top gate and the bottom gate, namely, the channel overlap region. The channel overlap region is between the channel non-overlap regions. The source region and the drain region are respectively disposed at the two sides of the channel non-overlap regions. The gate dielectric layers are respectively arranged between the top gate and the channel and between the bottom gate and the channel. Because of the asymmetric gate structure, smaller channel length is achieved when the device is opened, and larger channel length is achieved when the device is closed. The structure can ensure that the novel device has higher closing current and greater gate control capability at the closing moment and has higher opening current at the opening moment.