MOSFET and its manufacture

Abstract

The MOSFET features the channel inside the semiconductor substrate, the information channel area constituted with one doped semiconductor layer across the channel, the grid in and over the channel and around the information channel area with grid dielectric layer in between. The grid is separated from the side wall and bottom with one gapping wall and one insulating layer. The manufacture of the MOSFET includes following steps: forming channel filled with insulating layer on the substrate, eliminating the upper layer of the insulating layer, forming gapping wall on the side wall of channel,filling the channel with sacrificial layer; forming and defining one doped semiconductor layer on the substrate to form device area across the sacrificial layer; eliminating the sacrificial and forming grid dielectric layer on the surface of the device; forming conducting layer on the substrate filled into the channel and defining the conducting layer to form the grid; and forming source and drain on two sides of the grid.

Description

technical field [0001] The invention relates to a structure of a semiconductor device and a manufacturing method thereof, in particular to a metal-oxide-semiconductor field-effect transistor (MOSFET) and a manufacturing method thereof. Background technique [0002] With the shrinking of the line width of the metal oxide semiconductor (MOS) fabrication method, the leakage current between the source (Source) and the drain (Drain) away from the gate (Gate) increases accordingly. Although this leakage current can be reduced by a thin gate dielectric layer (Gate Dielectric), when the line width of the manufacturing method is reduced to less than 0.1μm, even a very thin gate dielectric layer cannot be reduced. leakage current. For this problem, Professor Chenming Hu of the University of California, Berkeley pointed out two solutions. One is to use a very thin semiconductor substrate to make MOSFETs, so that there is no longer any space in the substrate far away from the gate. Th...

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Problems solved by technology

Second, when forming the spacer between the raised source and drain sidewalls of the FinFET, the spacer material (silicon nitride) on the sidewall of the fin-shaped silicon layer is removed by overetching, so the sidewall of the fin-shaped silicon layer Defects will be generated at the wall, that is, the surface properties of the channel region will deteriorate, which will affect the performance of the device

Third, in order to reduce the source and drain resistance of FinFET, the conditions of the raised source and drain are not easy to control.

Fourth, because FinFET is a device with a vertical structure, the subsequent planarization method is not easy to carry out.

Fifth, since the fin-shaped silicon layer 120 of the FinFET must be narrow in width to reduce the leakage current, it needs to be defined by electron beam lithography, which has not yet been mass-produced, and the subsequent non-equal It is not easy to control the etching method

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