8results about How to "Increase parasitic capacitance" patented technology

The invention discloses a method for manufacturing a zeroth metal layer of an active region. The method comprises the following steps of: 1, providing a semiconductor substrate on which an active region contact hole opening forming process is completed; 2, forming an inner side wall on the side surface of the opening of the active area contact hole; and step 3, forming a BARC layer. And 4, performing a photoetching process to form a photoresist pattern to open the first ion implantation region. And step 5, removing the BARC layer in the first ion implantation region and performing first ion implantation to form a contact region at the bottom of the active region contact hole opening. And step 6, removing the BARC layer by adopting an ashing process, wherein the ashing process does not contain oxygen so as to ensure that the inner side wall is not oxidized. And 7, pre-cleaning is conducted, and in the pre-cleaning process, the inner side wall is reserved due to the fact that the inner side wall is not oxidized. And 8, forming a zeroth metal layer of the active region. According to the invention, the contact region can be formed to reduce the contact resistance, meanwhile, the size of the M0A can be ensured not to be enlarged, the parasitic capacitance between the M0A and the grid can be reduced, and the short circuit between the M0A and the grid can be prevented.

The invention discloses a VDMOS device of an integrated capacitor and a preparation method thereof, and relates to the technical field of microelectronics, and the VDMOS device comprises a drain electrode, a substrate and a drift region which are stacked in sequence; the first gate oxide layer is located on the upper surface of the drift region, and the orthographic projection of the first gate oxide layer is located in the orthographic projection range of the substrate in the direction perpendicular to the substrate; the grid electrode is located on the upper surface of the first gate oxide layer, and the orthographic projection of the grid electrode is located in the range of the orthographic projection of the first gate oxide layer; the second gate oxide layer covers the upper surface and the side surface of the gate electrode, and the orthographic projection of the second gate oxide layer is overlapped with the orthographic projection of the first gate oxide layer; the source electrode is located on the side face of a gate oxide layer composed of the first gate oxide layer and the second gate oxide layer, and the height of the source electrode is larger than that of the gate oxide layer; the insulating layer is positioned on the upper surface of the source electrode; the metal layer is located on the upper surface of the insulating layer, and the metal layer is connected with the grid electrode through the conductive hole. According to the invention, the switching rate of the VDMOS device can be reduced.

A semiconductor structure and a method for forming the semiconductor structure, the method comprising: providing a substrate; forming an initial fin structure on the substrate, the initial fin structure comprising a multi-layered initial sacrificial layer and a nanowire located on the initial sacrificial layer; forming source and drain openings at both ends of the initial fin structure in the extension direction, the source and drain openings exposing the sidewall surface of the initial fin structure; removing a portion of the initial sacrificial layer exposed by the source and drain openings to form a sacrificial layer, and forming a first groove on the sidewall of the sacrificial layer between adjacent nanowires; forming a first sidewall material layer in the first groove and on the sidewall of the nanowire, the first sidewall material layer having first ions; annealing the first sidewall material layer to diffuse the first ions into the nanowire to form a modified nanowire, the modified nanowire having the first ions. The performance of the semiconductor structure formed by the method is improved.

This invention relates to a semiconductor structure and its fabrication method. The semiconductor structure includes: a substrate; a transistor structure located on the substrate, the transistor structure including a gate structure and source and drain electrodes located on both sides of the gate structure; an interlayer oxide layer located on the substrate and covering the surface of the transistor structure; a contact plug penetrating the interlayer oxide layer and electrically connected to the source or drain electrode; and a sidewall structure located between the contact plug and the gate structure and covering the sidewall of the gate structure. The sidewall structure includes a first nitrided sidewall, a second nitrided sidewall, an oxide sidewall, and an air gap. The first nitrided sidewall, the oxide sidewall, and the second nitrided sidewall are sequentially stacked on the sidewall of the gate structure in a direction away from the gate structure. The air gap is located within the oxide sidewall, and the oxide sidewall communicates with the interlayer oxide layer. This invention can reduce the parasitic capacitance generated between the gate and the adjacent contact plug.

The embodiment of the invention provides a display panel and a display device, and the display panel comprises a substrate; the isolation structure is arranged on the substrate, an isolation opening and a light-transmitting opening are defined by the isolation structure, and the isolation opening is used for containing the light-emitting unit; and the conductive shielding layer is arranged on the substrate, the conductive shielding layer comprises a conductive shielding part, and the orthographic projection of the conductive shielding part on the substrate and the orthographic projection of the light-transmitting opening on the substrate are at least partially overlapped. The use performance of the display panel can be improved.

This invention discloses a semiconductor component with a finger-like metal wire-wound layout, comprising a semiconductor substrate, a first pad, and a second pad. The semiconductor substrate includes a first region and a second region with different polarities. The first pad is disposed on the first region. The first pad comprises multiple layers of metal and has a multilayer height. The second pad is disposed on the second region. The second pad comprises a single layer of metal and has a single-layer height. The multilayer height is greater than the single-layer height, such that the multilayer metal side area of ​​the first pad relative to the second pad is greater than the single-layer metal side area of ​​the second pad relative to the first pad.

A memory structure includes active columns of polysilicon formed over a semiconductor substrate, each active column including one or more vertical NOR strings, where each NOR string has thin film memory transistors sharing local source lines and local bit lines, the local bit line is connected by a segment of the segmented global bit line to a sense amplifier provided in the semiconductor substrate.

A common mode noise filter is provided that can improve the attenuation characteristics of common mode noise in a wide frequency range. The common mode noise filter disclosed in the present invention comprises: two magnetic parts (11) and a magnetic part (12) comprising a magnetic body; and a non-magnetic part (13) sandwiched by the magnetic parts (11) and the magnetic parts (12) in the stacking direction and comprising a non-magnetic body. It also comprises: two coils (14) and a coil (15) facing each other and built into the non-magnetic part (13); and a metal layer (16) formed inside at least one of the two magnetic parts (11) and the magnetic part (12) and connected to the ground. The metal layer (16) is located closer to the lower surface than the upper surface of the magnetic part (11), and is located closer to the upper surface than the lower surface of the magnetic part (12).