2results about How to "Increase parasitic capacitance" patented technology

This invention relates to a semiconductor structure and its fabrication method. The semiconductor structure includes: a substrate; a transistor structure located on the substrate, the transistor structure including a gate structure and source and drain electrodes located on both sides of the gate structure; an interlayer oxide layer located on the substrate and covering the surface of the transistor structure; a contact plug penetrating the interlayer oxide layer and electrically connected to the source or drain electrode; and a sidewall structure located between the contact plug and the gate structure and covering the sidewall of the gate structure. The sidewall structure includes a first nitrided sidewall, a second nitrided sidewall, an oxide sidewall, and an air gap. The first nitrided sidewall, the oxide sidewall, and the second nitrided sidewall are sequentially stacked on the sidewall of the gate structure in a direction away from the gate structure. The air gap is located within the oxide sidewall, and the oxide sidewall communicates with the interlayer oxide layer. This invention can reduce the parasitic capacitance generated between the gate and the adjacent contact plug.

This invention discloses a semiconductor component with a finger-like metal wire-wound layout, comprising a semiconductor substrate, a first pad, and a second pad. The semiconductor substrate includes a first region and a second region with different polarities. The first pad is disposed on the first region. The first pad comprises multiple layers of metal and has a multilayer height. The second pad is disposed on the second region. The second pad comprises a single layer of metal and has a single-layer height. The multilayer height is greater than the single-layer height, such that the multilayer metal side area of ​​the first pad relative to the second pad is greater than the single-layer metal side area of ​​the second pad relative to the first pad.