138results about How to "Increase parasitic capacitance" patented technology

The present invention Is a fabrication method for a short-channel Schottky-barrier field-effect transistor device. The method of the present invention includes introducing channel dopants into a semiconductor substrate such that the dopant concentration varies in the vertical direction and is generally constant in the lateral direction. A gate electrode is formed on the semiconductor substrate, and source and drain electrodes are formed on the substrate to form a Schottky or Schottky-like contact to the substrate.

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

An object is to provide a solid-state imaging device or a semiconductor display device with which a high-quality image can be taken. By performing operation using a global shutter method, a potential for controlling charge accumulation operation can be shared by all pixels. In addition, a first photosensor group includes a plurality of photosensors connected to a wiring supplied with an output signal, and a second photosensor group includes a plurality of photosensors connected to another wiring supplied with the output signal. A wiring for supplying a potential or a signal for controlling charge accumulation operation to the first photosensor group is connected to a wiring for supplying the potential or signal to the second photosensor group.

A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.

The present invention intends to prevent the communication distance from becoming shorter with a reduction in size of a coil antenna to the chip size and with a consequent decrease of an induced voltage. According to the present invention there is provided a semiconductor chip having a coil antenna and a circuit surface and adapted to transmit and receive signals by radio to and from an external device. The semiconductor chip has a configuration for increasing an electromagnetic coupling coefficient between the coil antenna and the external device. According to a concrete example thereof, a magnetic material is disposed, the coil antenna is formed by a stacked structure comprising plural conductor layers and insulating layers superimposed one on another, or the coil antenna is disposed outside an external form of a circuit of the semiconductor chip.

Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.

A touch sensor integrated type display device includes gate lines and data lines; a plurality of pixel electrodes respectively formed in pixel areas defined by crossings of the gate and data lines; a first electrode formed between first pixel electrodes and in parallel with a first gate line of the gate lines, the first pixel electrodes being adjacent to each other with the first gate line interposed therebetween; second electrodes formed between second pixel electrodes and arranged in a line in parallel with a second gate line adjacent to the first gate line, the second pixel electrodes being adjacent to each other with the second gate line interposed therebetween; and third electrodes, each of which is formed in parallel with the data lines and contacts the second electrodes, at least a portion of each of the third electrodes overlapping the first and second pixel electrodes.

A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are suited for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.

Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.

A touch sensor integrated type display device includes gate lines and data lines crossing over each other, pixel electrodes respectively formed in areas defined by crossing the gate lines and the data lines, first electrodes, each of which is formed between the pixel electrodes and in parallel with the gate line, the pixel electrodes being adjacent to each other with the gate line interposed therebetween, second electrodes formed in parallel with the data lines to overlap the pixel electrode, first routing wires connecting some of the first electrodes to form first electrode groups arranged in a first direction, second routing wires connecting another some of the first electrodes to form second electrode groups arranged in the first direction; and third routing wires connecting some of the second electrodes to form third electrode groups arranged in a second direction.

An inductor of the present invention includes a plurality of insulating layers being stacked and coil patterns respectively provided on predetermined layers of the insulating layers. The coil patterns are provided on at least two of the insulating layers, and electrically connected to each other. With this arrangement, it is possible to improve Q of the inductor without increasing the size of the inductor.

The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.

The present invention has an object to provide an active matrix substrate, a liquid crystal display panel, a liquid crystal display element, a liquid crystal display device, and a substrate for liquid crystal display panel, each capable of suppressing generation of uneven cell gap without increase in a parasitic capacitance of a wiring. The active matrix substrate of the present invention is an active matrix substrate including a spacer on a substrate, wherein the spacer includes a base layer and a covering layer, the base layer being buried in the covering layer.

A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.

A display device with favorable display quality is provided. A display portion where a plurality of pixels is arranged in a matrix is divided into Region A and Region B, i.e., regions on the upstream side and the downstream side of a scanning direction. A signal line for supplying an image signal is provided in each of Region A and Region B. Region A and Region B adjoin each other such that a boundary line showing the boundary between the regions is bent. Bending the boundary line suppresses formation of a stripe in a boundary portion. For example, in a given column, the total number of pixels electrically connected to a signal line in Region A is made different from the total number of pixels electrically connected to a signal line in Region B.

Provided are a semiconductor device and a method for fabricating the same. The semiconductor device can include a transistor structure, including a gate dielectric on a substrate, a gate electrode on the gate dielectric, a spacer at sidewalls of the gate electrode, and source/drain regions in the substrate; and an interlayer dielectric on the transistor structure where an air gap is provided in a region between the spacer, the interlayer dielectric, and the source/drain region of the substrate.

A metal oxide semiconductor (MOS) bandgap voltage reference circuit with a plurality of dummy bipolar junction transistors (BJTs) coupled to the mismatched parasitic substrate BJTs for improving parasitic capacitance matching, thereby improving startup behavior of the bandgap reference circuitry.

This invention relates to a platform technology of semiconductors combining advantages of the plane and mesa technologies to diffuse a deep junction at the edge of the PN junction to let it have a most possible high break-over voltage and erode silicon in the width sphere of an exhaust region of the outside of said junction to form a mesa structure, which can bear rather high break-over voltage to block the further expansion of the exhaust areas and reduce the capacitance of the PN junction, so the total break-over voltage of the collector junction of the transistor is increased due to the sum voltage shared by the mesa and the PN junction.

A transistor and a method of forming the same are disclosed. The method of forming the transistor comprises the steps of providing a semiconductor substrate consisting of a first region, a second region and a third region which are adjacent to one another; carrying out well region ion implantation, and forming a well region in the semiconductor substrate; carrying out channel ion implantation, and forming a first doped region in the surface of the well region in the first region; forming a gate structure on the semiconductor substrate and in the first region, the gate structure covering the first doped region in the first region; carrying out shallow doped ion implantation, forming a shallow doped source region in the semiconductor substrate and in the second region at one side of the gate structure, and forming a shallow doped drain region in the semiconductor substrate and in the third region at the other side of the gate structure; and forming an elevated source region on the shallow doped source region, and forming an elevated drain region on the shallow doped drain region. The method of the invention reduces the parasitic capacitance between the source and drain regions and the channel region and the substrate.