70results about How to "Implementation is particularly straightforward" patented technology

A case, includes a lid fitted with a first hinge portion, a concave bottom possibly including an inner frame intended to receive a trough containing the cosmetic product, the bottom or inner frame being fitted with a second hinge portion, the first and second hinge portions engaging to form a hinge, elements for closing the lid relative to the bottom or inner frame wherein: a) the closure elements include two magnets such that the lid is attracted towards the bottom inner frame for an opening angle α below a maximum angle of opening αL, b) the engagement is such that the maximum angle of opening αL is between 20° and 90°, c) the magnets are fully or partially concealed.

To form a layer separating two volumes of aqueous solution, there is used an apparatus comprising elements defining a chamber, the elements including a body of non-conductive material having formed therein at least one recess opening into the chamber, the recess containing an electrode. A pre-treatment coating of a hydrophobic fluid is applied to the body across the recess. Aqueous solution, having amphiphilic molecules added thereto, is flowed across the body to cover the recess so that aqueous solution is introduced into the recess from the chamber and a layer of the amphiphilic molecules forms across the recess separating a volume of aqueous solution introduced into the recess from the remaining volume of aqueous solution.

A low-power full-rate semidigital DLL architecture using an analog-based FSM (AFSM). The AFSM is a mixed-mode FSM in which analog integration is substituted for digital filtering, thus enabling a lower power implementation of the clock and data recovery function. An integrated voltage is converted to a digital code by an analog-to-digital converter (ADC), and the digital code is used either directly or after (low frequency) digital signal processing to control a controllable delay element, such as, a phase rotator, for data edge tracking.

A one-transistor (1T) NVRAM cell that utilizes silicon carbide (SiC) to provide both isolation of non equilibrium charge, and fast and non destructive charging / discharging. To enable sensing of controlled resistance (and many memory levels) rather than capacitance, the cell incorporates a memory transistor that can be implemented in either silicon or Sic. The 1T cell has diode isolation to enable implementation of the architectures used in the present flash memories, and in particular the NOR and the NAND arrays. The 1T cell with diode isolation is not limited to SiC diodes. The fabrication method includes the step of forming a nitrided silicon oxide gate on the Sic substrate and subsequently carrying out the ion implantation and then finishing the formation of a self aligned MOSFET.

A data processing system is provided in which processing circuitry performs at least one of a series of data processing operations in dependence upon a set of data values and control circuitry controls execution of the data processing operations. Control path error detection circuitry is provided for detecting a control path error associated with an error in operation of the control circuitry and data path error handling circuitry is arranged to handle recovery from errors in the data values. The control path error detection circuitry is configured to cause the data path error handling circuitry to perform recovery from detected control path errors enabling the series of data processing operations to continue despite the occurrence of the control path error. An associated method and computer program product are also provided.

The current invention describes a method for filtering an input image with a bilateral filter to produce an output image. The bilateral filter includes a spatial filter and a range filter. The method comprising the steps of: constructing an integral histogram from an input image including pixels, and wherein each pixel has an intensity; applying, for each pixel, the spatial filter to the integral histogram to produce a local histogram, each local histogram having a bin for a specified range of intensities of the pixels, each bin associated with a coefficient indicating a number of pixels in the specified range and an index to the coefficient; subtracting, for each bin in each local histogram, an intensity of the pixel from each index of the bin to produce a difference value; applying, for each bin, the range filter to each difference value to produce a response; scaling, each response by the corresponding coefficient to produce a scaled response; summing, for each local histogram, the scaled responses to produce a local response for the local histogram; summing, for each local histogram, the coefficients to produce a sum of the coefficient; and dividing, for each pixel, the local response by the sum of the coefficients to produce a response for the bilateral filter, which forms an output image.

A pipeline-based circuit with a postponed clock-gating mechanism and related driving method are disclosed for reducing power consumption, and the driving method does not deteriorate processing performance of the pipeline-based circuit. A pipeline-based circuit has a plurality of logic operators cascaded to form at least a pipeline, a pipeline control unit for generating at least a control signal to each logic operator for controlling whether one logic operator needs to pipe data to next logic operator, and a control value calculator for setting a valid bit of each logic operator following a currently activated logic operator according to the control signals generated from the pipeline control unit. When each logic operator begins operating, the related control value is used to determine whether or not a clock signal piping data of the present logic operator to next logic operator is gated to reduce power consumption. This postponed clock-gating mechanism avoids the degradation of pipeline clock speed limitation.