Post passivation interconnection schemes on top of the IC chips

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Description

RELATED PATENT APPLICATIONS [0001] This application is related to Ser. No. 09 / 251,183 filed on Feb. 17, 1999 which is a continuation-in-part of Ser. No. 09 / 216,791 filed on Dec. 21, 1998 assigned to a common assignee. This application is also related to attorney docket MEG00-008, Ser. No. ______, filing date ______.BACKGROUND OF THE INVENTION [0002] (1) Field of the Invention [0003] The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of post-passivation processing for the creation of conductive interconnects. [0004] (2) Description of the Prior Art [0005] Improvements in semiconductor device performance are typically obtained by scaling down the geometric dimensions of the Integrated Circuits, this results in a decrease in the cost per die while at the same time some aspects of semiconductor device performance are improved. The metal connections which connect the Integrated Circuit to other circuit or system components become of...

AI Technical Summary

Benefits of technology

[0029] A principal objective of the invention is to provide a method for the creation of interconnect metal that allows for the use of thick and wide metal.

[0031] Yet another objective of the invention is to provide a method that allows for the creation of long interconnect lines, whereby these long interconnect lines do not have high resistance or introduce high parasitic capacitance.

Problems solved by technology

This because an inorganic material cannot be deposited as a thick layer of dielectric because such a layer of dielectric would develop fissures and crack as a result fine-line interconnect metal is typically created using methods of sputter with resist etching or of damascene processes using oxide etch with electroplating after which CMP is applied.

Either one of these two approaches cannot create thick metal due to cost considerations or oxide cracking thick, wide interconnect lines can be created by first sputtering a thin metal base layer, coating and patterning a thick layer of photoresist, applying a thick layer of metal by electroplating, removing the patterned photoresist and performing metal base etching (of the sputtered thin metal base).

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