Interconnection line structure and forming method thereof

Abstract

The invention provides an interconnection line structure and a forming method of the interconnection line structure. The forming method of the interconnection line structure comprises the following steps of: providing a semiconductor substrate, wherein a semiconductor device is formed in the semiconductor substrate; forming an interlayer medium layer on the semiconductor substrate; forming a conductive layer on the interlayer medium layer; after the conductive layer is formed, forming grooves in the conductive layer and the interlayer medium layer, wherein the depth of the grooves is less than a thickness sum of the conductive layer and the interlayer medium layer, and a depth-to-width ratio of the grooves is more than 0.8; after the grooves are formed, depositing intermetallic medium layers, covering the conductive layer and filling the grooves through the intermetallic medium layers, and forming air gaps in the intermetallic medium layers. Compared with the prior art, the height of the grooves comprises the height of the conductive layer and a part of the height of the intermetallic medium layers, so that the depth-to-width ratio of the grooves between the adjacent interconnection lines is increased, the air gaps formed in the intermetallic medium layers inside the grooves are larger, stray capacitance is reduced and even removed, and the properties of the semiconductor device can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an interconnect structure and a method for forming the interconnect structure. Background technique [0002] Existing methods for forming metal interconnection structures include: [0003] refer to figure 1 A semiconductor substrate 100 is provided, on which a dielectric layer 101 and a metal layer 102 located on the dielectric layer 101 are formed. [0004] refer to figure 2 , form a patterned photoresist layer (not shown) on the metal layer 102, and use the patterned photoresist layer as a mask to etch the metal layer 102 to form a trench 103, and the grooves on both sides of the trench 103 The metal layer 102 also forms a metal interconnection line. [0005] refer to image 3 , deposit an inter-metal dielectric layer 104 , the inter-metal dielectric layer 104 fills the trench 103 and covers the metal layer 102 . [0006] However, when the semiconductor industry e...

AI Technical Summary

Problems solved by technology

However, when the process technology enters below 32nm, the role of the low-dielectric material in reducing parasitic capacitance is no longer obvious

Moreover, even for technologies with larger process nodes above 90nm, the existing method of completely filling the trenches between adjacent metal interconnection lines with the intermetallic dielectric layer cannot meet the requirements for the gap between adjacent metal interconnection lines. Minimize the parasitic capacitance between the technical requirements, such as some radio frequency integrated circuits

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