34results about How to "Improve RC delay" patented technology

A touch panel including a substrate, first touch electrodes, each of the first touch electrodes including first mesh patterns disposed on the substrate, an insulation layer disposed on the first touch electrodes, second touch electrodes, each of the second touch electrodes including second mesh patterns disposed on the insulation layer, first auxiliary mesh electrodes disposed on the substrate, the first auxiliary mesh electrodes being electrically connected to at least a portion of the corresponding second mesh patterns, and second auxiliary mesh electrodes disposed on the insulation layer, the second auxiliary mesh electrodes being electrically connected to at least a portion of the corresponding first me patterns.

The invention provides an interconnection line structure and a forming method of the interconnection line structure. The forming method of the interconnection line structure comprises the following steps of: providing a semiconductor substrate, wherein a semiconductor device is formed in the semiconductor substrate; forming an interlayer medium layer on the semiconductor substrate; forming a conductive layer on the interlayer medium layer; after the conductive layer is formed, forming grooves in the conductive layer and the interlayer medium layer, wherein the depth of the grooves is less than a thickness sum of the conductive layer and the interlayer medium layer, and a depth-to-width ratio of the grooves is more than 0.8; after the grooves are formed, depositing intermetallic medium layers, covering the conductive layer and filling the grooves through the intermetallic medium layers, and forming air gaps in the intermetallic medium layers. Compared with the prior art, the height of the grooves comprises the height of the conductive layer and a part of the height of the intermetallic medium layers, so that the depth-to-width ratio of the grooves between the adjacent interconnection lines is increased, the air gaps formed in the intermetallic medium layers inside the grooves are larger, stray capacitance is reduced and even removed, and the properties of the semiconductor device can be improved.

An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring.

A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping layer. The bit lines are disposed on a substrate within a cell region thereof, and the transistor is disposed on the substrate within a periphery region. The plugs are disposed in the dielectric layer, within the cell region and the periphery region respectively. The capping layer is disposed on the dielectric layer, and the capping layer disposed within the periphery region is between those plugs. That is, a portion of the dielectric layer is therefore between the capping layer and the transistor.

A thin film transistor (TFT) array substrate including a substrate, scan lines and data lines both disposed on the substrate, and pixel structures is provided. A plurality of pixel areas is defined by the scan lines and the data lines on the substrate. Each scan line has a driving signal input terminal and an end terminal. Each pixel area includes a first sub-pixel area and a second sub-pixel area. The pixel structures are respectively disposed in the pixel areas and driven by the scan lines and the data lines. Each pixel structure in the respective pixel area includes a first TFT corresponding to the first sub-pixel area and a second TFT corresponding to the second sub-pixel area. Besides, ratios of a channel width to a channel length of the second TFTs connected to the same scan line increase gradually from the driving signal input terminal to the end terminal.

A method of driving a display device including a plurality of pixels, the method including transmitting a plurality of data signals to first group pixels during a first scan period, simultaneously emitting light through the first group pixels according to a programmed data signal during a first light emitting period adjacent to the first scan period, transmitting a plurality of data signals to second group pixels, different from the first group pixels, during a second scan period, and simultaneously emitting light through the second group pixels according to a programmed data signal during a second light emitting period adjacent to the second scan period. A first field including the first scan period and the first light emitting period and a second field including the second scan period and the second light emitting period are temporally divided.

A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

A touch panel including a substrate, first touch electrodes, each of the first touch electrodes including first mesh patterns disposed on the substrate, an insulation layer disposed on the first touch electrodes, second touch electrodes, each of the second touch electrodes including second mesh patterns disposed on the insulation layer, first auxiliary mesh electrodes disposed on the substrate, the first auxiliary mesh electrodes being electrically connected to at least a portion of the corresponding second mesh patterns, and second auxiliary mesh electrodes disposed on the insulation layer, the second auxiliary mesh electrodes being electrically connected to at least a portion of the corresponding first mesh patterns.

A display device including a substrate, a gate driver disposed on the substrate and including a plurality of stages, a clock signal line disposed on the substrate, and transmitting a clock signal to at least one of the stages, a transistor disposed on the substrate, and a light blocking layer disposed between the substrate and the transistor and overlapping the transistor. The clock signal line includes a first conductive line and a second conductive line overlapping the first conductive line, and the first conductive line is disposed in the same layer as the light blocking layer.

A method of forming damascene patterns of semiconductor devices comprise forming a first insulating layer and contact plugs, formed in the first insulating layer, over a semiconductor substrate, forming an etch barrier layer and a second insulating layer over the first insulating layer, forming damascene patterns in the second insulating layer, forming a mask layer over the second insulating layer of other region except a region in which the contact plugs are formed so that the damascene patterns are exposed through the region in which the contact plugs are formed, removing the etch barrier layer under the exposed damascene patterns using an etching process employing the mask layer, and removing the mask layer.

A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash / flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.