34results about How to "Improve RC delay" patented technology

A method of driving a display device including a plurality of pixels, the method including transmitting a plurality of data signals to first group pixels during a first scan period, simultaneously emitting light through the first group pixels according to a programmed data signal during a first light emitting period adjacent to the first scan period, transmitting a plurality of data signals to second group pixels, different from the first group pixels, during a second scan period, and simultaneously emitting light through the second group pixels according to a programmed data signal during a second light emitting period adjacent to the second scan period. A first field including the first scan period and the first light emitting period and a second field including the second scan period and the second light emitting period are temporally divided.

A thin film transistor (TFT) array substrate including a substrate, scan lines and data lines both disposed on the substrate, and pixel structures is provided. A plurality of pixel areas is defined by the scan lines and the data lines on the substrate. Each scan line has a driving signal input terminal and an end terminal. Each pixel area includes a first sub-pixel area and a second sub-pixel area. The pixel structures are respectively disposed in the pixel areas and driven by the scan lines and the data lines. Each pixel structure in the respective pixel area includes a first TFT corresponding to the first sub-pixel area and a second TFT corresponding to the second sub-pixel area. Besides, ratios of a channel width to a channel length of the second TFTs connected to the same scan line increase gradually from the driving signal input terminal to the end terminal.

A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.

Disclosed is a TSV structure having insulating layers with embedded voids, including a chip layer, a dielectric liner and a conductive filler. There is at least a via reentrant from one surface of the semiconductor body of the chip layer. A plurality of air-gap cavities are formed on the sidewall of the via where the cavities have a depth-to-width ratio not less than one. The dielectric liner covers the sidewall of the via without filling into the air-gap cavities. The conductive filler is disposed in the via without filling into the air-gap cavities due to the isolation of the dielectric liner so as to form an air insulating layer with a plurality of enclosed voids embedded between the semiconductor body and the dielectric liner. Accordingly, RC Delay of the TSV structure can be improved.

A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a semiconductor layer disposed on the substrate and including at least a portion overlapping the gate electrode; a gate insulating layer disposed between the gate line and the semiconductor layer; and a source electrode and a drain electrode disposed on the substrate and facing each other over a channel region of the semiconductor layer. The gate insulating layer includes a first region and a second region, the first region corresponds to the channel region of the semiconductor layer, the first region is made of a first material, the second region is made of a second material, and the first material and the second material have different atomic number ratios of carbon and silicon.

The invention relates to the technical field of display, and particularly discloses a thin film transistor and a manufacturing method thereof, an array substrate, a display panel and an electronic device. The thin film transistor comprises a grid electrode, a grid electrode insulating layer, an active layer and a protective layer. The active layer is arranged on one side of the gate insulation layer, the gate is arranged on the other side, deviating from the active layer, of the gate insulation layer, the square resistance value of the gate is smaller than or equal to a preset square resistance value, and the gate at least comprises a first metal layer. The protective layer at least covers the exposed surface of the first metal layer to prevent the first metal layer from being oxidized. Inthis way, RC delay on the grid electrode can be reduced, and the problem that a display device is uneven in image flickering is solved.

A method of forming semiconductor memory device includes the following steps. Firstly, a substrate is provided and the substrate includes a cell region. Then, plural bit lines are disposed within the cell region along a first direction, with each of the bit line includes a tri-layered spacer structure disposed at two sides thereof. Next, plural of first plugs are formed within the cell region, with the first plugs being disposed at two sides of each bit lines. Furthermore, plural conductive patterns are formed in alignment with each first plugs. Following theses, a chemical reaction process is performed to modify the material of a middle layer of the tri-layered spacer structure, and a heat treatment process is performed then to remove the modified middle layer, thereto form an air gap layer within the tri-layered spacer structure.

A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

The embodiment of the invention discloses a forming method of a semiconductor device and a semiconductor device. The method comprises steps: depositing a first dielectric layer on a substrate, and depositing an etching stop layer on the first dielectric layer; depositing a second dielectric layer on the etching stop layer; etching the second dielectric layer, the etching stop layer and the first dielectric layer to form at least two pores with inclined side walls; depositing a metal material in each hole to form a first metal line; Etching the second dielectric layer between two adjacent firstmetal wires; a third dielectric layer is deposited over the etch stop layer to form an air gap between two adjacent first metal lines.