A manufacturing method for a semiconductor device

Abstract

The invention provides a manufacturing method for a semiconductor device. The manufacturing method of the invention comprises the following steps: firstly, a substrate is provided; secondly, a metal layer and a first dielectric layer are sequentially formed on the substrate through a deposition process; thirdly, the first dielectric layer and the metal layer are etched, and metal wires and first dielectric layer patterns on the metal wires are formed, and a part of the substrate is exposed; fourthly, an obstruction material layer is formed through a deposition process on the substrate and the first dielectric layer pattern; fifthly, the obstruction material layer is etched, and at least one obstruction body is formed between the adjacent metal wires; sixthly, a second dielectric layer is formed on the substrate, the first dielectric layer patterns, and the obstruction body, and gaps are formed between the metal wires and the obstruction body and / or in the second dielectric layer between the adjacent obstruction bodies. Through the adoption of the above method, the gaps can be formed in the second dielectric layer between the metal wires, and the dielectric constant of the second dielectric layer can be effectively reduced. A parasitic capacitance between the metal wires can be reduced and the condition of a RC delay of the interconnected metal wires is improved.

Description

technical field [0001] The present invention relates to a semiconductor manufacturing process, and more specifically, the present invention relates to a manufacturing method of a semiconductor device. Background technique [0002] With the continuous reduction of the feature size of semiconductor integrated circuits, the resistance capacitance delay (Resistor Capacitor, RC) of the back-end interconnection shows a significant increase trend. In order to reduce the RC delay, low dielectric constant materials are introduced, and copper interconnection replaces aluminum interconnection. become a mainstream technology. [0003] In production, with the reduction of the feature size of integrated circuits, the resistivity of copper interconnection lines will increase sharply, especially for the process of 45nm and below. However, there is currently no low-resistivity and cost-effective conductive material that can replace copper interconnects. The only way to reduce the parasitic ...

AI Technical Summary

Problems solved by technology

[0004] The present invention provides a manufacturing method of a semiconductor device to solve the problem of serious RC delay caused by the large parasitic capacitance between interconnection lines existing in the prior art, so as to achieve the purpose of improving the interconnection RC delay

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