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Semiconductor structure and its manufacture method

一种制造方法、半导体的技术,应用在半导体/固态器件制造、半导体器件、半导体/固态器件零部件等方向,能够解决产量下降、接触电阻上升等问题,达到改善产量、降低接触电阻、降低电迁移的效果

Active Publication Date: 2008-10-15
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These chemicals and oxygen can easily attack the copper wire 4 and the metal cap layer 8, and cause the contact resistance between the copper wire 4 and the via layer plug (not shown) thereon to increase.
This will result in a decrease in production

Method used

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  • Semiconductor structure and its manufacture method
  • Semiconductor structure and its manufacture method
  • Semiconductor structure and its manufacture method

Examples

Experimental program
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Embodiment Construction

[0028] The following will combine Figure 3-8B A process for manufacturing a semiconductor structure according to an embodiment of the present invention is described. image 3 Openings 26 are shown formed in dielectric layer 20 . Dielectric layer 20 is formed on substrate 18 . The substrate 18 may include a semiconductor substrate and various structures formed thereon, such as an etch stop layer, an interlayer dielectric layer, an intermetal dielectric layer, and the like. The semiconductor substrate may be a single crystal substrate or a compound semiconductor substrate on which active elements (not shown) such as transistors may be formed. Opening 26 may be a trench for forming a wire. In one embodiment, the dielectric layer 20 is preferably a low dielectric constant layer with a dielectric constant of less than about 3, more preferably an ultra-low dielectric constant layer with a dielectric constant of less than about 2.5. The dielectric layer 20 may include commonly u...

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PUM

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Abstract

An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring.

Description

technical field [0001] The present invention relates to integrated circuits, and more particularly to an interconnect structure and method for making the same. Background technique [0002] The damascene process has been widely used in the fabrication of metal lines and dielectric plugs in integrated circuits. The damascene process includes forming an opening in the IMD layer by conventional developing and etching processes, and then filling the opening with copper or copper alloy. After the excess metal material on the dielectric layer is removed by chemical mechanical polishing (CMP), the remaining copper or copper alloy can be used as a metal line and / or a dielectric layer plug. [0003] Copper has replaced aluminum as the primary wire material due to its lower electrical resistance. However, as the size of semiconductors continues to shrink and the current density increases, copper still has reliability problems of electro migration and stress migration. [0004] fig...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/522H01L23/532H01L21/768
CPCH01L21/76849H01L21/76856H01L21/76883
Inventor 张惠林沈定宇卢永诚
Owner TAIWAN SEMICON MFG CO LTD
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