3results about How to "Lower read latency" patented technology

The application provides a PLC programmable cement pole intelligent automatic demolding control method, which comprises collecting mold stress, vibration frequency, servo motor torque and pole surface temperature multi-source data, mapping the vibration frequency and the mold stress into high-dimensional features by relying on a temperature-driven thermal perception sparse coding dictionary, fusing the torque and the temperature to construct a real-time data frame; reconstructing the memory layout by predicting the state transition entropy, continuously storing the high-correlation data frame to form a main operation data area, establishing an independent emergency disposal data partition to store safety control parameters; correcting the state transition matrix in real time by means of the stress and the torque, performing predictive access on the pre-fetch data cluster, and solving the optimal control sequence; the PLC issues a demolding control instruction according to the optimal sequence, calculates a normalized torque margin to implement hierarchical control: when the margin is in the early warning interval, the emergency data retrieval priority is improved and a fine tuning instruction is output, and when the margin is out of limit, emergency braking is performed to ensure the safety of the demolding operation equipment and components.

This invention relates to the field of storage system IO performance optimization technology, and provides a method and device for redirecting data aggregation, comprising: identifying random small IO data from written IO requests, aggregating and writing to backend storage objects, and constructing a storage mapping relationship in an index table; traversing backend storage objects storing random small IO data, and allocating data originating from the same logical address space to the same target backend storage object using a hash algorithm; sequentially writing the data allocated to the same target backend storage object into the contiguous physical space of the target backend storage object, and updating the mapping relationship in the index table; repeating steps S2 and S3 before reaching a preset termination trigger condition, using a different hash algorithm each time step S2 is repeated; when reading data, retrieving the storage mapping relationship from the index table, and aggregating the read requests corresponding to data located in the same backend storage object before reading them all at once.

The application discloses a memory operation system compliant with DDR memory access timing, and belongs to the field of memory and scientific calculation, comprising: a row-level parallelism driven timing termination mechanism, which utilizes row nonlinear charging characteristics to reduce tail delay of tRCD and tRP; and a row block interleaving, row-column collaborative vector-matrix multiplication (VMM) access mechanism, which reduces tRAS and overlaps CL timing parameters without increasing peripheral column ADC precision overhead, and reduces cross-point RAM internal core delay; the proposed row access and column access collaborative optimization memory hardware design can enable VMM operation compliant with DDR memory access timing in a memory-centric manner, so as to realize efficient hardware execution of low-delay, high-bit-width data-intensive scientific calculation (computational physics) loads.