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2results about How to "Lower read latency" patented technology

A method and apparatus for redirecting data aggregation

ActiveCN121029092BImprove read performanceEliminate read amplification effects
This invention relates to the field of storage system IO performance optimization technology, and provides a method and device for redirecting data aggregation, comprising: identifying random small IO data from written IO requests, aggregating and writing to backend storage objects, and constructing a storage mapping relationship in an index table; traversing backend storage objects storing random small IO data, and allocating data originating from the same logical address space to the same target backend storage object using a hash algorithm; sequentially writing the data allocated to the same target backend storage object into the contiguous physical space of the target backend storage object, and updating the mapping relationship in the index table; repeating steps S2 and S3 before reaching a preset termination trigger condition, using a different hash algorithm each time step S2 is repeated; when reading data, retrieving the storage mapping relationship from the index table, and aggregating the read requests corresponding to data located in the same backend storage object before reading them all at once.
Owner:CHINA ELECTRONICS CLOUD DIGITAL INTELLIGENCE TECH CO LTD

An in-memory operation system compliant with DDR memory access timing

ActiveCN116610604Bimprove performancereduce settling delayComputer architectureEngineering
The application discloses a memory operation system compliant with DDR memory access timing, and belongs to the field of memory and scientific calculation, comprising: a row-level parallelism driven timing termination mechanism, which utilizes row nonlinear charging characteristics to reduce tail delay of tRCD and tRP; and a row block interleaving, row-column collaborative vector-matrix multiplication (VMM) access mechanism, which reduces tRAS and overlaps CL timing parameters without increasing peripheral column ADC precision overhead, and reduces cross-point RAM internal core delay; the proposed row access and column access collaborative optimization memory hardware design can enable VMM operation compliant with DDR memory access timing in a memory-centric manner, so as to realize efficient hardware execution of low-delay, high-bit-width data-intensive scientific calculation (computational physics) loads.
Owner:HUAZHONG UNIV OF SCI & TECH