An Asymmetric Dual-Gate Junctionless Field-Effect Transistor

Abstract

The invention discloses a novel asymmetric double-gate junctionless field effect transistor comprising a top gate, a bottom gate, a source region, a drain region, gate dielectric layers, a channel overlap region, and channel non-overlap regions. The top gate and the bottom gate are respectively disposed in an upper position and in a lower position of a channel, and are of an asymmetric structure. There is an overlap region between the top gate and the bottom gate, namely, the channel overlap region. The channel overlap region is between the channel non-overlap regions. The source region and the drain region are respectively disposed at the two sides of the channel non-overlap regions. The gate dielectric layers are respectively arranged between the top gate and the channel and between the bottom gate and the channel. Because of the asymmetric gate structure, smaller channel length is achieved when the device is opened, and larger channel length is achieved when the device is closed. The structure can ensure that the novel device has higher closing current and greater gate control capability at the closing moment and has higher opening current at the opening moment.

Description

technical field [0001] The invention relates to a device for semiconductor integrated circuits, mainly a novel asymmetric double-gate junction-free field-effect transistor. Background technique [0002] As the size of CMOS devices shrinks, junctionless devices are a good device structure to meet the challenges of size reduction. For CMOS devices, a good transfer characteristic curve is very important, which mainly depends on the subthreshold slope (SS) of the device, the leakage-induced barrier lowering (DIBL) characteristics, the size of the threshold voltage, the leakage current (I OFF ) size, drive current (I ON ) and other factors. These characteristics belong to the basic electrical characteristics of the device. In addition, junctionless devices also have other characteristics that need to be studied, such as variability, reliability, AC characteristics, and so on. Junctionless devices encounter many variability problems when shrinking in size, such as threshold vo...

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Problems solved by technology

[0004] However, when the size of the device is reduced to a greater extent (approaching less than 20nm), the characteristics of the junction-free device will also show many shortcomings.

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