Three-dimensional semiconductor device and manufacturing method thereof

Abstract

The invention discloses a three-dimensional semiconductor device which comprises a plurality of storage units and a plurality of selection transistors. Each of the plurality of storage units comprises a channel layer which is distributed along a direction perpendicular to the surface of a substrate; a plurality of interlayer insulating layers and a plurality of grid stack structures which are alternately stacked along the side wall of the channel layer; a plurality of floating gates which are arranged between the plurality of interlayer insulating layers and the side wall of the channel layer; a drain electrode which is arranged at the top of the channel layer; and a source electrode which is positioned in the substrate between two adjacent storage units of the plurality of storage units. According to the three-dimensional semiconductor device and a manufacturing method thereof, the floating gates are arranged at the side walls of the vertical channels, and the starting of the source and drain regions generated on the side walls of the channels due to induction is controlled through the coupling between the gate electrodes and the floating gates, thereby improving induction efficiency and intensity of the source and drain regions, reducing source and drain resistance of the storage units, and improving read current and read speed of a storage array.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a three-dimensional semiconductor device and a manufacturing method thereof. Background technique [0002] In order to improve the density of memory devices, the industry has made extensive efforts to develop methods of reducing the size of two-dimensionally arranged memory cells. As the size of memory cells in two-dimensional (2D) memory devices continues to shrink, signal collisions and interference can increase significantly, making it difficult to perform multi-level cell (MLC) operations. In order to overcome the limitations of 2D memory devices, the industry has developed memory devices with a three-dimensional (3D) structure to increase integration density by three-dimensionally arranging memory cells on a substrate. [0003] Specifically, a multilayer stack structure (for example, a plurality of ONO structures alternating with oxides and nitrid...

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Problems solved by technology

[0004] As the device size is further reduced to, for example, 22nm or even 10nm nodes, the resistance of the channel region made of polysilicon and other materials increases significantly. The problems of reduced efficiency, reduced induction intensity, and increased series resistance directly affect the read current and read speed of the memory array

In extreme cases, the potential far from the read node of the memory cell (such as the bit line BL at the top of the stack structure or the source metal silicide in the substrate) may not be sufficient to induce source-drain regions in the channel region, thereby causing the entire The storage unit fails and the data cannot be read

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