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Method for forming 3D NAND flash memory

A flash memory and graphics technology, applied in the manufacturing of electrical components, electro-solid devices, semiconductor/solid-state devices, etc., can solve the problems of increased process difficulty, no advantages of 1YNAND products, and increased product reliability requirements, and can reduce the size, Increase process difficulty and improve the effect of equivalent storage area

Active Publication Date: 2016-11-16
WUHAN XINXIN SEMICON MFG CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, one of the main reasons why 3D NAND is difficult to achieve mass production is that the storage density per unit area is not high enough, so that the cost per unit storage unit is not superior to that of planar 1Y NAND products, or even higher
For 3D NAND, the method of increasing storage density is mainly by increasing the number of stacked layers, but this method not only increases the difficulty of the process, but also leads to higher reliability requirements of the product

Method used

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  • Method for forming 3D NAND flash memory
  • Method for forming 3D NAND flash memory
  • Method for forming 3D NAND flash memory

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Embodiment Construction

[0028] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

[0029] Such as figure 1 As shown, the present embodiment relates to a method for forming a 3D NAND flash memory, and the method specifically includes the following steps:

[0030] In step S1, a photomask is provided, and in the photomask, a predetermined number of rows of vertical hole patterns are formed in a row of gate lines; preferably, the predetermined number of rows is 9 rows, that is, in the photomask, In a row of gate lines, 9 rows of vertical hole patterns are formed, such as image 3 structure shown.

[0031] figure 2 It is a schematic structural diagram of an existing photomask forming vertical holes. It is obvious that the arrangement of vertical holes formed by the photomask in this embodiment is more optimized, which can save area and increase storage density.

[0032] In ste...

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PUM

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Abstract

The invention relates to the manufacturing technical field of a semiconductor, and particularly to a method for forming a 3D NAND flash memory. By optimization of structures of channel holes and gate lines, nine rows of perpendicular hole patterns can be placed in one gate line; then after the processing of the channel holes is finished, the separation of the channel holes in the upper and lower rows can be realized through etching of a first trench so as to reduce the required area of a second trench and overlap; finally, the separate line connection of each CH BL in the same layer of GL SL is realized through a back section dual-pattern etching process so as to effectively reduce the size of an effective storage cell; and therefore, under the premise of not increasing the technological difficulty, the equivalent storage area is improved by about 35-40% by optimization of the planar process structure and the back section line connecting process.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming 3D NAND flash memory. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits and existing development technology limits. In this context, in order to solve the difficulties encountered in planar flash memory and to seek lower production costs per unit storage unit, various three-dimensional flash memory structures have emerged as the times require. However, the biggest challenge facing three-dimensional memory is how to increase the storage density per unit area to achieve a lower cost than planar flash memory. [0003] At present, one of the main reasons why 3D NAND is difficult to achieve mass production is that the storage density per ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8247H01L27/115H10B41/27H10B41/35H10B43/27H10B43/35H10B69/00
CPCH10B41/27H10B43/27
Inventor 高晶曾明
Owner WUHAN XINXIN SEMICON MFG CO LTD
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