32results about How to "Lower pinch-off voltage" patented technology

The invention discloses a high-voltage junction field effect transistor structure. An inversion layer is filled into a deep channel of a body region of the structure. The invention further discloses a manufacture method of the high-voltage junction field effect transistor structure (HV JFET) structure. The manufacture method comprises the steps of manufacturing the inversion layer in the deep channel of the body region through a photoetching and ion implantation process while manufacturing a substrate trap of a manufacture body region or the inversion layer of a drain terminal drifting region in the HV JFET conventional manufacture process. By filling one opposite type of impurities into the deep channel of the JFET body region, the impurity concentration of the channel of the JFET body region is reduced on a basis that any photoetching layer is not increased, the channel is easily used up, and accordingly the pinch-off voltage of an HV JFET device is effectively reduced.

Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.

The invention discloses a pinch-off voltage reducing structure of a dual-channel high voltage junction field effect transistor (FET) and a manufacturing method of the pinch-off voltage reducing structure of the dual-channel high voltage junction FET. A well region provided with a channel region and a drift region is formed in a silicon substrate, a drift region inversion layer is arranged in the drift region, a gate region is formed on the outer side of the channel region, a channel region inversion layer is arranged in the channel region, the transverse width of the channel region inversion layer is longer than the transverse width of the channel region, and two ends of the channel region inversion layer are connected with the gate region. A drain electrode leading-out terminal is formed in the drift region, a source electrode leading-out terminal is formed in the channel region, a gate electrode leading-out terminal is formed in the gate region, and a substrate leading-out terminal is formed in the substrate region. The drift region, the drain electrode leading-out terminal and the source electrode leading-out terminal are in a second conductivity type, the substrate, the drift region inversion layer, the channel region inversion layer, the gate region, the gate leading-out terminal and the substrate leading-out terminal are in a first conductivity type, and electrodes are led out from the leading-out terminals. According to the pinch-off voltage reducing structure of the dual-channel high voltage junction FET and the manufacturing method of the pinch-off voltage reducing structure of the dual-channel high voltage junction FET, impurities which are opposite in type are implanted inside the channel region to form double channels, namely an upper channel and a lower channel, the opposite impurities are arranged in the channel region at the same time, and therefore each channel can be exhausted more easily, and pinch-off voltage is lowered.

The present invention discloses a junction field effect transistor which comprises a P type substrate, a P type buried layer, N type buried layers arranged at two sides of the P type buried layer, an N type epitaxial layer, a first isolation structure, a second isolation structure, a third isolation structure and a fourth isolation structure which are arranged on the N type epitaxial layer, a source electrode area arranged between the first isolation structure and the second isolation structure, a first N well area arranged under the source electrode area, a gate electrode area arranged between the second isolation structure and the third isolation structure, a drain electrode area arranged between the third isolation structure and the fourth isolation structure, a second well area arranged under the source electrode area, and at least one P type field limit ring which is arranged above the N type epitaxial layer and is between the source electrode area and the drain electrode area. According to the above junction field effect transistor, the effect of Triple RESURF can be realized, the pinch-off voltage can be reduced effectively, and the purpose of low pinch-off voltage is realized. The invention also discloses the preparation method of the junction field effect transistor.

The invention provides a semiconductor device and a manufacturing method thereof, and belongs to the technical field of power semiconductors. The semiconductor device is formed by multiple interdigitally connected cells with the same structure/ The cell structure comprises a second conductivity type light doped substrate, a first conductivity type light doped epitaxial layer, a diffusion second conductivity type well region, a first and third heavily doped regions having the first conductivity type, a second heavily doped region having the second conductivity type, a depletion type channel region, an oxide medium layer, a metal cathode, a metal anode and a back metal electrode. The forward withstand voltage and constant current characteristics of the device are optimally designed through the form of a metal field plate and injection of the second conductivity type doped region; the used second conductivity type light doped substrate has the effect of assisting the depletion of the first conductivity type light doped epitaxial layer and the conductive channel so as to improve the withstand voltage of the device and reduce the pinch-off voltage and realize better constant current capability and higher breakdown voltage; and finally the designed withstand voltage of the device is 460V and the pinch-off voltage is below 4V.

The invention discloses a junction field effect transistor. A channel region is arranged between two adjacent same-doped well regions, the channel region is doped through diffusion of the two adjacent well regions, and well regions with the opposite doping types are arranged above the channel region and used for longitudinal depleting the channel region. According to the junction field effect transistor, the doping concentration of the channel region can be reduced, the pinch-off voltage of the channel region is lowered, and thus the pinch-off voltage of the channel region can be adjusted, a small pinch-off voltage is obtained and extra cost does not need to be added. The width requirement of the channel region can be met just by adjusting the widths of the two adjacent same-doped well regions on the two sides of the channel region, and thus the channel current of the device can be adjusted; moreover, the channel current can be enlarged easily, and thus a large channel current is obtained. The invention further discloses a manufacturing method of the junction field effect transistor.

A semiconductor device includes a semiconductor substrate, a first well region, and a second well region. The semiconductor substrate has a first conductivity type. The first and second well regions are disposed in the semiconductor substrate. The first and second well regions have a second conductivity type that is opposite to the first conductivity type. The semiconductor device also includes a first top layer and a second top layer. The first top layer is disposed in the semiconductor substrate. The first top layer extends from the first well region to the second well region. The first top layer has the first conductivity type. The second top layer is disposed in the semiconductor substrate and on the first top layer. The second top layer extends from the first well region to the second well region. The second top layer has the second conductivity type.

A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.

The invention discloses a current stabilizer tube comprising a P-type epitaxial layer, two first N-type areas, a longitudinal conduction trench and a third N-type area. The P-type epitaxial layer is formed on the front surface of a P+ silicon substrate. The first N-type areas are formed in the P-type epitaxial layer. The part, between the first N-type areas forms the longitudinal conduction trench. The third N-type area is formed in the P-type epitaxial layer in the bottom area of the longitudinal conduction trench. When a device operates, the third N-type area helps increase the ability to consume the P-type epitaxial layer in the bottom area of the longitudinal conduction trench, pinch-of voltage of the device can be reduced thereby; increase in the width of the longitudinal conduction trench leads to increase in conduction current; by adjusting the pinch-off voltage of the device through the third N-type area, the pinch-off voltage can be kept unchanged or lower while conduction current is increased, and reliability of the device is improved thereby. The invention further discloses a manufacturing method of the current stabilizer tube.

The invention discloses an improved groove-type Schottky rectifier device and a manufacturing method thereof. The improved groove-type Schottky rectifier device disclosed by the invention comprises a first conduction type substrate, a first conduction type conducting layer, grooves, conducting polycrystalline silicon, a gate insulator layer and a metal electrode layer, wherein a second conduction type area is arranged inside the upper surface layer of the first conduction type conducting layer between every two adjacent grooves; and the metal electrode layer is arranged on the first conduction type conducting layer, the conducting polycrystalline silicon and the second conduction type area. The backward voltage resisting capacity is improved, and meanwhile the problem that the forward voltage drop becomes large caused by small groove distance is solved.