32results about How to "Lower pinch-off voltage" patented technology

The invention discloses a semiconductor device comprising a junction type field effect transistor and a manufacturing method thereof. The semiconductor device comprises a junction type field effect transistor, wherein the junction type field effect transistor comprises a semiconductor underlay, an epitaxial layer, a body region, a source electrode region and a grid region, wherein the semiconductor underlay is provided with a first doping type and taken as a drain region of the junction type field effect transistor; the epitaxial layer is located on the semiconductor underlay and provided with a first doping type; the body region is located in the epitaxial layer and provided with a second doping type, and the types of the second doping type and the first doping type are reverse; the source electrode is located in the epitaxial layer and provided with a first doping type; and the grid region is located in the body region and provided with the second doping type, wherein the junction type field effect transistor further comprises a shielding layer, the shielding layer is provided with the second doping type, which is located in the epitaxial layer, and is also located in a conduction path between the source electrode region and the drain region. With the adoption of the shielding layer, a new pinch-off region is generated in the junction type field effect transistor, so as to reduce pinch-off voltage.

The invention discloses a nitride high electron mobility ratio transistor extension configuration which adopts compound insulated layer and preparation method, by inserting GaN insulated layer between the AlGaN potential barrier layer and the insulated layer of the AlGaN / GaN high electron mobility ratio transistor, it can decrease the ratio that hot electron enters into the AlGaN potential barrier effectively, and decrease the dispersion of alloy, increase the transmission property of electron, so the frequency property of the transistor can be improved, besides it is good for the realization of component ohm contacting craft and decreasing the hardness of craft of producing high property component.

The invention discloses a pinch-off voltage reducing structure of a dual-channel high voltage junction field effect transistor (FET) and a manufacturing method of the pinch-off voltage reducing structure of the dual-channel high voltage junction FET. A well region provided with a channel region and a drift region is formed in a silicon substrate, a drift region inversion layer is arranged in the drift region, a gate region is formed on the outer side of the channel region, a channel region inversion layer is arranged in the channel region, the transverse width of the channel region inversion layer is longer than the transverse width of the channel region, and two ends of the channel region inversion layer are connected with the gate region. A drain electrode leading-out terminal is formed in the drift region, a source electrode leading-out terminal is formed in the channel region, a gate electrode leading-out terminal is formed in the gate region, and a substrate leading-out terminal is formed in the substrate region. The drift region, the drain electrode leading-out terminal and the source electrode leading-out terminal are in a second conductivity type, the substrate, the drift region inversion layer, the channel region inversion layer, the gate region, the gate leading-out terminal and the substrate leading-out terminal are in a first conductivity type, and electrodes are led out from the leading-out terminals. According to the pinch-off voltage reducing structure of the dual-channel high voltage junction FET and the manufacturing method of the pinch-off voltage reducing structure of the dual-channel high voltage junction FET, impurities which are opposite in type are implanted inside the channel region to form double channels, namely an upper channel and a lower channel, the opposite impurities are arranged in the channel region at the same time, and therefore each channel can be exhausted more easily, and pinch-off voltage is lowered.

The invention relates to semiconductor technology, in particular to a lateral constant current diode. In the lateral constant current diode described in the present invention, a lightly doped P-type region and a heavily doped P-type region are introduced into the N-type well region to form a P-type well region, thereby modulating the surface electric field, increasing the breakdown voltage, and lightening The doped P-type region can assist in depleting the N-type well region, making the channel easier to pinch off and quickly enter the constant current region, so that the constant current diode has a lower pinch-off voltage, and the deeper heavily doped P-type region shortens the The channel length improves the constant current of the constant current diode. The beneficial effect of the present invention is that the breakdown voltage of the lateral constant current diode can be effectively improved, and at the same time, the channel can be more easily pinched off, and can quickly enter the constant current region, so that the lateral constant current diode has a lower pinch-off voltage, and the lateral constant current diode can be effectively improved. The constant current of the constant current diode. The invention is especially suitable for lateral constant current diodes.

The invention discloses a high voltage JFET device and a processing method of the same. A P substrate is provided with a deep N-well. From a cutaway view angle, a field oxide is on the deep N-well, and the two ends of the field oxide are a JFET source area and a drain area. The field oxide is covered with a poly-silicon field plate. The deep N-well is divided into two sections: a first deep N-well section and a second deep N-well section wherein the first deep N-well section contains the JFET source area and the second deep N-well section contains the JFET drain area and a P injection layer. The first deep N-well section and the second deep N-well section are independent from each other. Between the first deep N-well section and the second deep N-well section is a P-well. The P-well shares the sizes with both the two deep N-well sections. Also between the first deep N-well section and the second deep N-well section is the P injection layer. The P injection layer, right under the P well, also shares sizes with with both the two deep N-well sections. The JFET device provided by the invention is provided with adjustable pinch-off voltage and at the same time, with high breakdown voltage as well. The invention also discloses a processing method for such a high voltage JFET device.

The invention provides an organic thin-film transistor, which includes: a substrate, a gate electrode, an isolation layer, an organic semiconductor layer, a leakage electrode and a source electrode. The organic thin-film transistor has structure that is one of top contact type, bottom contact type and top gate type. The organic thin-film transistor has characteristics in that: also includes a connection layer, said connection layer is composed of one or more of cavity type organic semiconductor material. Aims of the invention is to optimize manufacturing process of the organic thin-film transistor, increase the organic thin-film transistor performance, reduce greatly the organic thin-film transistor cost, and reduce technological requirement and cost for the organic thin-film transistor industrialization.

The invention is a method for manufacturing AlGaN / AlInN compound barrier gallium nitride field effect transistor. The process steps are divided into sequentially growing a nucleation layer, an AlGaN buffer layer, a GaN channel layer, an AlN isolation layer and an AlInN layer on a substrate. The lower barrier layer; the AlGaN upper barrier layer is covered on the AlInN lower barrier layer to form a composite barrier; the AlGaN upper barrier layer on the AlGaN upper barrier layer is thinned except for the area reserved for gate electrodes by microelectronic technology Layer; making source electrode and drain electrode on the thinned part; making gate electrode on the area reserved for making gate electrode on the AlGaN upper barrier layer. Advantages: broaden and increase the potential barrier, improve the channel well structure, enhance the two-dimensional characteristics of the electron gas, and the strong negative polarized charge on the AlGaN / AlInN heterointerface increases the strength of energy band clipping, and meets the requirements of ohmic contact and Schottky potential different heterostructure requirements throughout the barrier, under-gate trench, and off-gate trench.

The invention belongs to the semiconductor device field and discloses a junction field effect transistor. According to the junction field effect transistor, a back grid is formed between a trench and a P substrate of the JFET (junction type field effect transistor) and is corresponding to the position of a positive grid, and as a result, when negative voltage is applied to the grids, depletion regions of a positive grid PN junction and a negative grid PN junction do not horizontally extend, but vertically extend with the increase of the negative voltage, so that small pinch-off voltage can be obtained; drain-source voltage is mainly borne by horizontal extension of the depletion regions, and P type lightly-doped regions which are adjacent to a source are formed between the trench and the P substrate of the JFET, so that the distribution of an electric field in the trench of the JFET is more uniform, and N type lightly-doped regions which are located below a drain are formed between the trench and the P substrate of the JFET, and thus, breakdown of a PN junction formed by the trench and the P substrate of the JFET, which occurs at the bottom of a drain end, can be avoided, and as a result, high drain-source breakdown voltage can be obtained. With the junction field effect transistor adopted, contradictions among three parameters, namely, the pinch-off voltage, the drain-source breakdown voltage and current conduction capacity, can be alleviated.

The invention discloses a JFET (junction field-effect transistor) device and a manufacturing method thereof. A drift region is formed by a doped first deep trap region, in a second conduction type, formed on a doped substrate in a first conduction type; a body region comprises a channel region and a doped second deep trap region in the second conduction; the channel region is positioned between the first deep trap region and the second deep trap region and comprises more than two doped third deep trap regions, in the second conduction type, in evenly-spaced arrangement, and doping impurities of a space area between each two adjacent third deep trap regions are formed by diffusion impurities of the adjacent third deep trap region; process conditions of the three deep trap regions are identical. Pinch-off voltage of the JFET device can be adjusted by adjustment of impurity concentration of the deep trap regions, width of each space area and number of the space areas. By the JFET (junction field-effect transistor) device and the manufacturing method thereof, the pinch-off voltage can be lowered, convenience in adjustment of the pinch-off voltage is achieved, and requirements on various different pinch-off voltages can be met.

The invention discloses a high-voltage junction field effect transistor structure. An inversion layer is filled into a deep channel of a body region of the structure. The invention further discloses a manufacture method of the high-voltage junction field effect transistor structure (HV JFET) structure. The manufacture method comprises the steps of manufacturing the inversion layer in the deep channel of the body region through a photoetching and ion implantation process while manufacturing a substrate trap of a manufacture body region or the inversion layer of a drain terminal drifting region in the HV JFET conventional manufacture process. By filling one opposite type of impurities into the deep channel of the JFET body region, the impurity concentration of the channel of the JFET body region is reduced on a basis that any photoetching layer is not increased, the channel is easily used up, and accordingly the pinch-off voltage of an HV JFET device is effectively reduced.