Semiconductor device comprising junction type filed effect transistor and manufacturing method thereof

Abstract

The invention discloses a semiconductor device comprising a junction type field effect transistor and a manufacturing method thereof. The semiconductor device comprises a junction type field effect transistor, wherein the junction type field effect transistor comprises a semiconductor underlay, an epitaxial layer, a body region, a source electrode region and a grid region, wherein the semiconductor underlay is provided with a first doping type and taken as a drain region of the junction type field effect transistor; the epitaxial layer is located on the semiconductor underlay and provided with a first doping type; the body region is located in the epitaxial layer and provided with a second doping type, and the types of the second doping type and the first doping type are reverse; the source electrode is located in the epitaxial layer and provided with a first doping type; and the grid region is located in the body region and provided with the second doping type, wherein the junction type field effect transistor further comprises a shielding layer, the shielding layer is provided with the second doping type, which is located in the epitaxial layer, and is also located in a conduction path between the source electrode region and the drain region. With the adoption of the shielding layer, a new pinch-off region is generated in the junction type field effect transistor, so as to reduce pinch-off voltage.

Description

technical field [0001] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device including a junction field effect transistor and a method of manufacturing the same. Background technique [0002] figure 1 A cross-sectional view of a conventional N-channel junction field effect transistor (JFET) 100 is shown. The JFET 100 includes an N+ type drain region 101 (usually a substrate), an N-type epitaxial layer 102 located on the N+ type drain region 101, a P-type body region 103 located in the N-type epitaxial layer 102, and a P-type body region 103 located in the N+ type drain region 101. The N+ type source region 104 in the − type epitaxial layer 102 and between the P type body regions 103 , and the P+ type gate region 105 located in the P type body region 103 . The JFET 100 also includes an interlayer dielectric layer (ILDL) 106, a source contact 107 electrically connected to the N+ type so...

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Problems solved by technology

[0005] In order to solve the problems described above, the present invention proposes an improved semiconductor device including a JFET and its manufacturing method, wherein the source region and the gate region of the JFET can maintain a sufficient distance, and the pinch-off voltage of the JFET can be reduced at the same time

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