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Junction field effect transistor and preparation method thereof

A technology of field effect transistors and junctions, applied in the preparation of junction field effect transistors, in the field of junction field effect transistors, can solve the problem of high pinch-off voltage

Active Publication Date: 2015-12-09
CSMC TECH FAB2 CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Conventional JFETs have a high pinch-off voltage

Method used

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  • Junction field effect transistor and preparation method thereof
  • Junction field effect transistor and preparation method thereof
  • Junction field effect transistor and preparation method thereof

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Embodiment Construction

[0019] In order to make the objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings. In this specification and drawings, reference signs N and P assigned to layers or regions indicate that these layers or regions include a large number of electrons or holes, respectively. Further, the reference marks + and − assigned to N or P indicate that the concentration of the dopant is higher or lower than in layers not so assigned to the marks. In the following description of the preferred embodiments and the drawings, similar components are assigned similar reference numerals and redundant descriptions thereof are omitted here.

[0020] A junction field effect transistor, comprising: a P-type substrate; a P-type buried layer and an N-type buried layer placed on the P-type substrate. Wherein, the N-type buried layer is respectively pla...

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Abstract

The present invention discloses a junction field effect transistor which comprises a P type substrate, a P type buried layer, N type buried layers arranged at two sides of the P type buried layer, an N type epitaxial layer, a first isolation structure, a second isolation structure, a third isolation structure and a fourth isolation structure which are arranged on the N type epitaxial layer, a source electrode area arranged between the first isolation structure and the second isolation structure, a first N well area arranged under the source electrode area, a gate electrode area arranged between the second isolation structure and the third isolation structure, a drain electrode area arranged between the third isolation structure and the fourth isolation structure, a second well area arranged under the source electrode area, and at least one P type field limit ring which is arranged above the N type epitaxial layer and is between the source electrode area and the drain electrode area. According to the above junction field effect transistor, the effect of Triple RESURF can be realized, the pinch-off voltage can be reduced effectively, and the purpose of low pinch-off voltage is realized. The invention also discloses the preparation method of the junction field effect transistor.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a junction field effect transistor and a preparation method of the junction field effect transistor. Background technique [0002] BCD is a monolithic integration process technology, which can prepare bipolar transistors (BipolarJunctionTransistor) CMOS and DMOS devices on the same chip. In the BCD process, a Junction Field Effect Transistor (JFET) is a very important type of device. Using a Junction Field Effect Transistor can easily build a start-up module and a constant current source module. For a JFET, its pinch-off voltage is one of the most critical parameters. Conventional JFETs have a high pinch-off voltage. Contents of the invention [0003] Based on this, it is necessary to provide a junction field effect transistor with low pinch-off voltage to solve the above problems. [0004] Also provided is a preparation method of the junction field effect transistor....

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/808H01L21/337
Inventor 祁树坤张广胜
Owner CSMC TECH FAB2 CO LTD
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